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CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Materials and Substrates Research and Development is sponsored by National Institute of Standards and Technology (NIST). This Notice of Funding Opportunity (NOFO) seeks applications for new research and development (R&D) activities to establish and accelerate domestic capacity for advanced packaging substrates and substrate materials, a key technology for producing microelectronics systems.
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National Advanced Packaging Manufacturing Program | NIST https://www. nist.
gov/chips/research-development-programs/national-advanced-packaging-manufacturing-program CHIPS FOR AMERICA / Research & Development Programs National Advanced Packaging Manufacturing Program CHIPS National Advanced Packaging Manufacturing Program (NAPMP) Awards The CHIPS NAPMP has finalized $300 million in award funding under its first Notice of Funding Opportunity (NOFO) for advanced substrates and material research to Absolics Inc., Applied Materials Inc., and Arizona State University to bolster U.S. leadership in advanced packaging and enable new technologies to be validated and transitioned at scale to U.S. manufacturing.
These awards will help establish a self-sustaining, high-volume, domestic, advanced packaging industry where advanced node chips are both manufactured and packaged in the United States. You can learn more about the awardees here . “Advanced packaging” refers to many chips with diverse functions assembled tightly together on a substrate in two or three dimensions at extremely fine dimensions.
This method achieves function, performance, and power savings far greater than can be achieved with conventionally packaged chips on a printed circuit board. Recent advances in artificial intelligence, for example, would not be possible without advanced packaging. Advanced packaging can be a transformative capability that helps U.S. manufacturers compete globally, but there are many technological challenges to solve.
The CHIPS Research and Development Office has established the CHIPS National Advanced Packaging Manufacturing Program to address these challenges, including: How do we design and assemble chips so tightly that they behave like a single traditional large chip, but with the production efficiency and cost savings of advanced packaging? How do we supply power to and dissipate heat from such tightly coupled assemblies?
How do we test and repair such complex assemblies? How do we ensure their reliability since traditional methods of visual inspection cannot be performed on such small, tightly packaged dimensions? Investments in semiconductors will not succeed without investments in advanced packaging.
The CHIPS and Science Act offers a once-in-a-generation opportunity to establish a domestic competitive advanced packaging capability in semiconductor manufacturing. In addition, the CHIPS NAPMP will help train semiconductor personnel and students in relevant technologies and feed these developments into domestic manufacturing facilities.
The CHIPS NAPMP will work closely with the CHIPS National Semiconductor Technology Center , the semiconductor-related CHIPS Manufacturing USA Program , the CHIPS Metrology Program , and U.S. industry and academia to make this vision a reality.
The CHIPS NAPMP will enable the development of a robust domestic advanced packaging ecosystem by: Accelerating the transfer of innovations in packaging, equipment, and process development into manufacturing; Driving the development of digital tools to reduce the time and cost of advanced packaging engineering; and, Establishing and supporting partnerships among industry, academia and training entities, and government to contribute to an advanced packaging workforce.
Based on current listing details, eligibility includes: Eligible applicants include domestic for-profit and non-profit organizations; accredited domestic institutions of higher education including community and technical colleges; and state, local, territorial, and Indian tr… Applicants should confirm final requirements in the official notice before submission.
Current published award information indicates Not specified Always verify allowable costs, matching requirements, and funding caps directly in the sponsor documentation.
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NIST AI-Focused Manufacturing USA Institute is sponsored by National Institute of Standards and Technology (NIST). NIST announced an open competition for a new Manufacturing USA institute focused on the use of artificial intelligence (AI) to increase the resilience of U.S. manufacturers. The institute will be required to obtain cost-share funds from nonfederal sources.
SBIR FY 2026 Phase I Notice of Funding Opportunity is sponsored by National Institute of Standards and Technology (NIST). The SBIR FY 2026 Phase I Notice of Funding Opportunity is a grant from the National Institute of Standards and Technology (NIST) that supports small businesses in developing innovative technologies aligned with NIST research priorities.
Digital Cities' Innovation Accelerator Small Grant Program is sponsored by U.S. State Department's Bureau of Cyberspace and Digital Policy (CDP). These small grants activate the private sector to deliver novel and innovative solutions to civic challenges. Projects must address a sub-national public service or infrastructure need AND incorporate trusted U.S. digital based solutions, empowering municipalities to improve public service delivery.
This NOFO provides an opportunity to all FY 2018 NIST SBIR Phase I awardees to submit a Phase II application following completion of Phase I. This NOFO provides instructions for FY 2019 NIST SBIR Phase II application preparation and submission requirements. In Phase II, work from Phase I that exhibits potential for commercial application is further developed. Phase II is the R&D or prototype development phase. To apply for a Phase II award, each Phase I awardee will be required to submit a comprehensive application outlining the proposed research and a detailed plan to commercialize the final product. Each NIST Phase II award is for up to $400,000 and up to a 24-month period of performance. One year after completing the Phase II R&D activity, the awardee shall be required to report on its commercialization activities. Up to an additional $6,500 may be requested for Technical and Business Assistance (TABA); see Section 5.11 for more information about TABA. Funding Opportunity Number: 2019-NIST-SBIR-02. Assistance Listing: 11.620. Funding Instrument: CA. Category: ST. Award Amount: Up to $400K per award.
Research on Circular Economy, Smart Manufacturing, and Energy-Efficient Microelectronics is sponsored by U.S. Department of Energy (DOE) Advanced Materials & Manufacturing Technologies Office (AMMTO). This funding opportunity supports innovative technology R&D across the manufacturing sector with a focus on circular economy, smart manufacturing, and energy-efficient microelectronics. While the stated deadline for full applications has passed, AMMTO frequently issues similar solicitations, and this highlights a relevant area of interest for the DOE.