DARPA Wants Memory That Survives Deep Space and a Reactor Core: The $1.2M Direct-to-Phase-II NVM Topic Closing August 19
July 11, 2026 · 6 min read
Granted Research Team · Editorial policy
Most memory chips die quietly. Leave a commercial NOR Flash part in the cold of deep space, or bolt it near a reactor core, or fly it through the radiation belts, and it will corrupt, latch up, or simply stop holding a charge. That failure mode is one of the quiet constraints on everything the United States wants to do in space, in nuclear energy, and in strategic defense — and DARPA has just put $1.2 million on the table to fix it. The Non-Volatile Memory for Extreme Environments topic — DPA26BZ04-DV017 — asks small businesses to deliver a co-packaged, temperature-hard, radiation-tolerant NOR Flash memory system that keeps working from -269°C to +600°C. It opened July 22 and closes August 19, 2026, and its structure tells you almost everything about who it is really for.
Direct-to-Phase-II is the headline, not the money
The specification that matters most is not the dollar figure. It is the phrase Direct-to-Phase-II (DP2). There is no Phase I feasibility study here, no $150,000 warm-up, no six months to sketch an approach and see if it holds. DARPA is skipping straight to the build, and it is doing so deliberately, because the agency does not believe this is a problem you can start from a blank page and solve in a proposal cycle.
DP2 topics come with a gate that most SBIR solicitations do not: you must document that you have already done Phase-I-equivalent work. For this topic, that means concrete evidence — initial hardware demonstrations of the proposed memory technology, plus simulated or experimental data validating feasibility across the temperature and radiation envelope. In plain terms, DARPA is asking to see a chip, or at minimum defensible silicon-level data, before you apply. A team that reads this topic on July 22 and decides to enter the rad-hard memory business is not a candidate. A team that has been grinding on extreme-environment non-volatile memory for years and has the wafers to prove it is exactly the intended audience.
This is the single most important strategic fact about the topic. The four-week window from open to close is not really four weeks of work — it is four weeks to package years of prior work into a credible DP2 proposal. If you have that prior work, the timeline is tight but achievable. If you don't, no amount of proposal effort closes the gap, and the honest move is to note the topic for a future cycle and start building the evidence base now.
What the specs actually demand
The technical bar is worth reading closely, because it explains why the field is small.
- Temperature range: -269°C to +600°C. That lower bound is roughly 4 kelvin — the temperature of liquid helium, the regime of deep-space cryogenics and superconducting systems. The upper bound is hot enough to sit near a reactor or inside a hypersonic vehicle's electronics bay. Commercial parts are typically rated for -40°C to +125°C. DARPA is asking for an operating envelope more than five times wider than what the market ships.
- Radiation tolerance: on the order of 2 Mrad total ionizing dose and survivability to a dose rate around 5×10¹¹ rad/s. Total ionizing dose is the slow accumulation that degrades a part over a mission; dose rate is the instantaneous pulse — the kind a nuclear event produces — that latches up or destroys unhardened silicon in microseconds. Meeting both at once is the hard part.
- Density and speed: a Phase I-equivalent baseline of at least 1Mb at 10MHz, scaling in Phase II to a 32Mb system holding >1MHz across the full temperature range, with endurance around 1 million read/write cycles and density above 1 million bits per square millimeter.
- The deliverable is hardware, not a report: ten packaged 32Mb prototype units, full fabrication process documentation, radiation and temperature characterization data, and interface boards with test instructions so the government can independently evaluate the parts.
Every one of those requirements is individually achievable by someone in the rad-hard semiconductor world. The difficulty — and the reason DARPA is paying for it — is meeting all of them in one co-packaged system. Radiation hardening usually costs you temperature range; extending temperature range usually costs you density or endurance. The topic is a request to stop trading these against each other.
Why this is a national-capability problem, not a gadget
It is tempting to read an extreme-environment memory topic as niche. It is the opposite of niche — it is infrastructure for three national priorities at once.
Space. Every satellite, deep-space probe, and lunar or Martian system needs non-volatile memory that holds state through thermal cycling and cumulative radiation without the mass penalty of heavy shielding. Shielding is weight, weight is launch cost, and inherent radiation hardness is how you buy performance back. As U.S. space activity scales — commercial constellations, cislunar logistics, defense assets in higher orbits — memory that survives without a lead box becomes a throughput constraint on the whole enterprise.
Nuclear energy. The new generation of advanced reactors and the sensors that monitor them need electronics that function in heat and radiation fields where commercial parts fail. Memory that survives near a core enables instrumentation and control systems that today have to be placed at a distance, cabled, and shielded.
Strategic defense. DARPA frames the underlying challenge as the "memory wall" — the point at which processing speed is bottlenecked by how fast and how reliably you can reach memory. In resilient military computing, that wall is worse, because the environment is actively hostile. Radiation-hardened, high-temperature memory is a prerequisite for high-performance computing that keeps running through exactly the conditions it is designed to operate in.
A single 32Mb prototype is not the point. The point is a domestic capability to manufacture memory that does not exist commercially at this envelope — and to keep that capability inside U.S.-owned, U.S.-controlled companies.
Eligibility and the export-control reality
The baseline SBIR rules apply, plus one that carries real weight here:
- For-profit, U.S.-owned and U.S.-controlled small business, 500 employees maximum including affiliates.
- The principal investigator's primary employment must be with the company — the standard SBIR 51% rule.
- ITAR/EAR export-control compliance is not optional. Radiation-hardened and extreme-environment electronics sit squarely in controlled-technology territory. A team without an export-control posture — knowing which data is controlled, who on the team may access it, how foreign nationals are handled — is not ready to execute this award regardless of how good the silicon is. Build the compliance answer into the proposal, not after the award.
How a qualified team should sequence the next four weeks
If you have the prior hardware work, here is the realistic path from now to August 19:
- Assemble the feasibility evidence first. The DP2 gate is prior demonstration. Before writing narrative, marshal your existing hardware results, radiation test data, and temperature characterization into the documentation package that proves you belong in a Phase II. If that package is thin, the proposal cannot rescue it.
- Write the technical volume around the trade you have solved. Reviewers know radiation hardness and temperature range fight each other. The winning proposal names that tension explicitly and shows, with data, how your approach holds both without collapsing density or endurance.
- Make the 32Mb Phase II path concrete. DARPA wants ten packaged units and a fabrication process, not a lab curiosity. Show the manufacturing route from your current demonstration to deliverable prototypes.
- Resolve export control and U.S.-control questions up front. These are pass/fail items. Do not leave them as an afterthought in the final days.
The Non-Volatile Memory for Extreme Environments topic is one of the more honest DP2 solicitations of the cycle: it tells you plainly that it is looking for a team that already exists, already has silicon, and already understands why this is hard. For the small number of companies that fit that description, $1.2 million and a 24-month runway to a national-capability deliverable is closing on August 19, 2026 — and the clock started the day it opened.
For DARPA's other Direct-to-Phase-II topic this cycle, see Granted's deep dive on the FALCON ML/LLM fusion topic. For every federal small-business deadline in one place, see the SBIR & STTR Deadlines 2026 guide.