DARPA's Quietest FY26 SBIR Topic Is a Rad-Hard Flash Chip That Survives -250°C to +600°C — and It Closes August 19

The AI topics get the headlines. When DARPA released the fourth tranche of its FY2026 SBIR Broad Agency Announcement, the attention went — predictably — to the two artificial-intelligence topics: FALCON and Art of Novel Signals, which we covered in depth in our analysis of DARPA's Defense Sciences Office drop. But the third topic in the same release is, for the right company, the most interesting of the three — precisely because almost nobody can do it.

Non-Volatile Memory for Extreme Environments (topic DPA26BZ04-DV017, Multi-X office) asks small businesses to build something that does not currently exist in any commercial catalog: a co-packaged, non-volatile memory system that holds data reliably across a temperature range from -250°C to +600°C and tolerates radiation levels that would corrupt or destroy an ordinary chip. It opened July 22, 2026 and closes August 19, 2026 — the same tight, roughly four-week window as the rest of Release 4. If you build hardened electronics, this topic is worth a hard look, because the competitive field for it is small by definition.

What the topic actually asks for

The objective, in DARPA's own framing, is to "develop and demonstrate a co-packaged temperature-hard (-250°C to +600°C) and radiation-tolerant NOR Flash memory system." Every clause in that sentence is load-bearing, so it is worth unpacking.

NOR Flash is the flavor of non-volatile memory used when a system needs to execute code directly from storage — reliable, byte-addressable, the kind of memory that boots a spacecraft's flight computer or holds the firmware for a downhole sensor. It is not the high-density NAND in a consumer SSD; it is the durable, deterministic memory that mission-critical embedded systems depend on.

Temperature-hard from -250°C to +600°C describes an 850-degree operating span. The cold end (-250°C, roughly 23 kelvin) is the environment of deep space and cryogenic instrumentation. The hot end (+600°C) is the environment of a jet engine's hot section, a hypersonic vehicle's skin, or a downhole drilling tool near geothermal heat. Commercial industrial-grade parts are typically rated to about +85°C or +125°C. Even the toughest automotive and military parts top out far below 600°C. Standard silicon simply stops behaving like silicon at those extremes.

Radiation-tolerant means the memory must retain and correctly read its data through the total-ionizing-dose and single-event effects of a space or nuclear environment — the accumulated damage and the sudden bit-flips that cosmic rays and energetic particles inflict on unshielded electronics.

Co-packaged is the systems-engineering catch. DARPA does not want three separate research results — a cold-tolerant cell here, a rad-hard controller there, a high-temperature interconnect somewhere else. It wants an integrated memory system in a single package that survives all of these conditions simultaneously. That integration requirement is what separates a serious proposal from a wish list.

Why this is a real gap, not a manufactured one

It is fair to ask whether a topic this exotic reflects a genuine need or a research office chasing a curiosity. In this case the need is concrete and growing.

Defense and space systems are pushing into environments that commercial electronics were never designed for. Hypersonic vehicles generate skin temperatures that cook conventional avionics. Space systems — especially the proliferated small-satellite constellations the Department of Defense is now fielding by the hundreds — need radiation tolerance without the mass and cost of traditional heavily-shielded rad-hard parts. Cryogenic systems for quantum sensing and advanced instrumentation need memory that works near absolute zero. Downhole energy and geothermal exploration need electronics that survive sustained high heat. In every one of these domains, the memory is often the weakest link: the processor and the sensors can be hardened, but if the non-volatile memory holding the code and the calibration data fails, the whole system fails.

The commercial market does not solve this problem because the volumes are tiny and the engineering cost is enormous. That is exactly the market failure SBIR exists to bridge — high strategic value, low near-term commercial pull, technical risk too high for a small company to absorb alone. A functioning extreme-environment NOR Flash system would have immediate pull across space, hypersonics, nuclear, and energy-exploration markets, which is the kind of dual-use commercialization story DARPA program managers want to hear.

How DARPA SBIR economics work — and why the clock matters

DARPA runs its SBIR program differently from the civilian agencies, and understanding the mechanics is half the battle.

DoD SBIR Phase I awards are typically capped around $250,000 (agencies often award in the $250K–$295K band) for a feasibility study lasting a few months. Phase II scales up to roughly $1.8–$2 million for prototype development. Crucially, DARPA and other DoD components frequently offer a Direct-to-Phase-II (D2P2) path for teams that can already demonstrate Phase-I-level feasibility — letting a mature team skip straight to the prototype-scale award of up to about $2 million. Always confirm the exact ceilings and whether D2P2 is offered against the official topic instructions in the BAA, because these figures vary by topic and are set in the solicitation, not by the general program.

The strategic reality of DARPA SBIR is that it is not "free money for research." It is fast, milestone-driven, and unforgiving of teams that need to invent their approach after the award. A four-week open window is a filter: it selects for companies that already have relevant materials, device physics, or packaging work in hand and can turn a pre-existing capability into a targeted proposal. If you are reading about NOR Flash device physics for the first time this week, this is not your cycle. If you have been working on wide-bandgap semiconductors, silicon-carbide or silicon-on-insulator devices, high-temperature packaging, or rad-hard-by-design memory, this topic may map directly onto work you have already done.

Who is actually positioned to win this

The eligible field for DPA26BZ04-DV017 is narrow, and that is the opportunity. Realistic contenders cluster in a few categories:

• Wide-bandgap and specialty-semiconductor firms working in silicon carbide, gallium nitride, or silicon-on-insulator — material systems that hold up where bulk silicon degrades.
• Rad-hard-by-design houses that already build radiation-tolerant memory or logic for space and strategic systems and can extend the design into the temperature extremes.
• Advanced-packaging and MEMS companies whose core competency is the co-packaging and thermomechanical integration that the topic explicitly demands.
• University-spinout teams with novel non-volatile-memory physics (ferroelectric, resistive, or emerging-cell approaches) that may tolerate temperature and radiation better than floating-gate flash — a route worth exploring under the STTR framing if a strong academic partner is involved.

If your company sits in one of these lanes, the winning move is to lead with your existing, demonstrable capability and frame the SBIR as the integration step that turns component-level results into DARPA's co-packaged system. Proposals that read as "we will figure out the physics" lose to proposals that read as "here is the physics we have already validated, and here is the specific integration risk this award retires."

The strategy for a four-week window

Three things separate a competitive submission from a wasted effort in a window this short.

First, register now — do not wait. Every DoD SBIR submission requires an active SAM.gov registration, a SBIR Company Registry entry, and accounts in the DoD submission system. These registrations can take days to weeks to clear. A team that starts the paperwork the week before the deadline will not make it, no matter how strong the technology.

Second, read the official topic instructions in the BAA, not the summary. The public topic listing gives you the objective and the topic number; the actual solicitation document specifies the award ceilings, the phase structure, whether Direct-to-Phase-II is available, the deliverables, and the evaluation criteria. Everything strategic lives in that document.

Third, write to the co-packaging requirement explicitly. The most common way to lose an integration-focused topic is to propose three disconnected research threads. DARPA reviewers for this topic will be looking for a credible path to a single package that survives all conditions at once. State your integration approach, name the specific failure modes at each temperature and radiation extreme, and describe how your architecture retires each one.

The bottom line

DARPA's Non-Volatile Memory for Extreme Environments topic (DPA26BZ04-DV017) is the kind of SBIR opportunity that rewards deep, narrow expertise. It asks for a co-packaged, radiation-tolerant NOR Flash system that works from -250°C to +600°C — a capability that does not exist off the shelf and that a shrinking set of specialized firms is genuinely positioned to build. It opened July 22 and closes August 19, 2026, a four-week window that filters hard for readiness. If you build hardened electronics for space, hypersonics, nuclear, or downhole environments, the competitive field here is thin, the strategic pull is real, and the deadline is close. Start the registrations today, pull the official BAA instructions, and write to the integration challenge — because that is the part almost nobody can actually do.