CHIPS AI/AE for Rapid, Industry-informed Sustainable Semiconductor Materials and Processes (CARISSMA) Competition

CHIPS AI/AE for Rapid, Industry-informed Sustainable Semiconductor Materials and Processes (CARISSMA) Competition is sponsored by NIST - National Institute of Standards and Technology. Aims to develop sustainable semiconductor materials and processes using AI and advanced engineering.

CHIPS AI/AE for Rapid, Industry -informed Sustainable Semiconductor Materials and Processes (CARISSMA) Competition Federal Funding Opportunity Funding Opportunity Number: U.S. Department of Commerce (DOC ), National Institute of Standards and Technology (NIST) FY 202 5 CHIPS AI/AE for Rapid, Industry -informed Sustainable Semiconductor Materials and Processes (CARISSMA) Competition Notice of Funding 202 5-NIST -CHIPS -AIAE -Sustainability -01 Subject to the availability of funds, t his NOFO seeks applications for industry -informed, university -based artificial intelligence -powered autonomous experimentation ( AI/AE ) collaborations, including research and development, education and workforce development, and related activities relevant to sustainable semiconductor materials and processes .

If successful, awards made under th is NOFO will support the long -term viability of next -generation domestic semiconductor manufacturing, accelerating the discovery, design, synthesis, and adoption of materials and processes, and the development of new researchers needed to meet the industry’s technology, economic, and sustainability goals. Announcement Type: Initial .

Funding Instrument Type : Awards under this program will be made as other transaction agreements as authorized , in 15 U.S.C. § Assistance Listing Number (formerly known as the CFDA Award Period of Performance : Project period of performance up to five (5) years.

2 Goals and Objectives: Through awards made under this NOFO, the CHIPS Research and Development Office (CHIPS R&D) aims to achieve the following objectives: 1) Accelerate research into and delivery of targeted, industry -relevant, sustainable semiconductor materials and processes through the application of AI/AE; 2) Propagate models for incorporating sustainability metrics into semiconductor industry materials design and discovery, in addition to continued advancement in power, performance, area, cost , or other relevant 3) Expand the capabilities of emerging research institutions and other emerging R&D participants through cohesive , innovative teams of universities, industry, government labs, and 4) Build an exceptional workforce of university graduates and faculty with AI/AE R&D expertise.

If successful, CHIPS R&D investments under this NOFO should demonstrate that new sustainable semiconductor materials and processes, meeting industry needs, can be designed and adopted for industry testing within five years.

Further, the investment should accelerate a step -change in the number of universities, researchers, and graduates participating in the U.S. semiconductor R&D Under this NOFO, eligible applicants are domestic accredited institutions of higher education and domestic non -profit or for -profit organization s that manage consortia of accredited institutions of higher education .

A domestic entity is one that is incorporated within the United States (including a U.S. territory) with its principal place of business in the United States (including a U.S. territory).

Eligible applicants may submit only one concept paper and, if invit ed, one full Eligible subrecipients under this NOFO include accredited institutions of higher education; for -profit organizations or non -profit organizations; State, local, territorial, and Tribal governments; Federally Funded Research and Development Centers; Federal entities; foreign partners; and other entities eligible to participate 3 as applicants.

Eligible subrecipients may participate in Vendors selling goods or services in the ordinary course of business are not considered subrecipients Available Funding: CHIPS R &D anticipates that the total Federal funds available under this NOFO to be approximately $100 Cost Share or Match: Non -federal cost share is not required in this program .

However , CHIPS R&D encourages applicants to detail in their applications opportunities for optional co - investment , which may include industry -provided expertise, intellectual property, facility access, or other forms of partner co -investment during the award period of performance. For more information on optional co - investment s, see Section 3. 2 .

Estimated Number of Awards : Multiple awards in amounts ranging from approximately $20 to $ 40 million per award in Federal funds , with a period of performance of up to five (5) years , per award are anticipated under this NOFO , for projects varying in Submission Dates and Times: Relevant dates in the application process for this NOFO are listed below in Table 1 and described in the text that Table 1.

Key Dates for 202 5-NIST -CHIPS -AIAE - NOFO Publication Date October 30, 2024 Information al Webinar November 8, 2024 Meeting November 15, 2024 January 13 , 202 5, 11:59 Full application deadlines invited applicants at the The U.S. Department of Commerce may amend this NOFO at any time. It may also close th is funding opportunity with at least 60 days’ notice. Any changes will be communicated via https://www.

grants. gov and Concept papers and full applications must be submitted electronically through Grants. gov .

Paper or emailed submissions will not be accepted. Prospective applicants and subrecipients are required to have an active registration in the System of Award Management (https://sam.

gov/content/home) prior to submitting an application and throughout the award term and are encouraged to begin the process of registering as early Informational Webinar : Information al Webinar : The National Institute of Standards and Technology (NIST) CHIPS for America Research and Development Office (CHIPS R&D) will host an informational webinar on November 8, 2024 , to provide general information regarding this NOFO, offer general guidance on preparing applications, and answer questions.

Proprietary technical discussions about specific project ideas will not be permitted during the webinar, and CHIPS R&D staff will n ot critique or provide feedback on any specific project ideas while they are being developed by an applicant, brought forth during the webinar, or at any time before the deadline for applications.

However, questions about th is funding opportunity, eligibil ity requirements, evaluation and award criteria, selection process, and the general characteristics of a competitive application will be addressed during the webinar and by e -mail for inquiries sent to research@chips. gov with “202 5-NIST - CHIPS -AIAE -Sustainability -01 Questions” in the subject line.

There is no cost to attend the webinar, but participants must register in advance.

Participation in the webinar is not required and will not be considered in the review and selection process described in Section Proposers ’ Day and Teaming Meetings: In addition to the informational webinar described above, CHIPS R&D plans to host one or more Proposers’ Days to promote awareness of the funding opportunity and 5 provide a forum for organizations to identify p rospective partners.

Information about the event can be found on the CHIPS for America events website . Concept Papers: The submission of a concept paper is required. Concept papers will be accepted only through Grants.

gov. Concept papers must be received at Grants. gov no later than 11:59 p. m.

Eastern Time, on January 13 , 202 5. Concept papers received after the specified deadline will not be reviewed or considered. Applicants should be aware, and factor into their concept paper submission planning, that the Grants.

gov system closes periodically for routine maintenance. Applicants should visit Grants. gov for information on any scheduled closures.

Please note that an a ctive registration in the System for Award Management is required to submit concept paper materials through Full Applications: Full applications will be accepted only from those applicants that are invited after completion of the concept paper evaluation. Full applications will be accepted only through Grants. gov. The full application deadline will be communicated to invited applicants at the time of invitation.

Full applications received after the specified deadline will not be reviewed or considered. Agency Contacts: Any inquiries regarding this NOFO must be submitted to the agency points of contact listed in Section 7 of this NOFO . Applicants m ay submit questions by e -mail to the appropriate agency point of contact with “202 5- NIST -CHIPS -AIAE -Sustainability -01” in the s ubject line.

Programmatic and Technical Questions : Agreements Rules and Regulations : Additional Information: CHIPS R&D has a public website that includes a Frequently Asked Questions page and other information pertaining to this funding opportunity. 6 1 PROGRAM DESCRIPTION ................................ ................................

................................ .............. 10 1.

1 Program Overview ................................ ................................ ................................

......................... 10 1. 1.

1 CHIPS R&D Mission and Goals ................................ ................................ .........................

10 1. 1. 2 NOFO Objectives ................................

................................ ................................ ................

11 1. 2 Definitions ................................ ................................

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12 1. 3 Background ................................ ................................

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13 1. 3. 1 Challenge: Economic Pressure ................................

................................ ............................ 14 1.

3. 2 Challenge: Materials Co -optimization and Time to Deployment ................................ .......

15 1. 3. 3 Challenge: Limited Research Workforce ................................

................................ ............ 15 1.

3. 4 Opportunity: AI/AE ................................ ................................

................................ ............ 16 1.

3. 5 Opportunity: Emerging Research Institutions ................................ ................................

..... 16 1. 4 Funding Opportunity Detailed Description ................................

................................ .................... 17 1.

4. 1 Operational Areas ................................ ................................

................................ ............... 17 1.

4. 2 Materials Classes and Applications ................................ ................................

.................... 18 1. 4.

3 Co -optimization Targets ................................ ................................ ................................

..... 18 1. 4.

4 Programmatic Targets ................................ ................................ ................................

......... 20 1. 4.

5 Phases of Work and SMART Milestones ................................ ................................ ...........

22 1. 4. 6 Project Team Capabilities and Structure ................................

................................ ............. 23 1.

5 OA -Specific Activities and Deliverables ................................ ................................ .......................

25 1. 5. 1 OA1: Convening, Roadmapping, and Technology Transfer ................................

............... 25 1. 5.

2 OA2: AI/AE Infrastructure and Research ................................ ................................ ...........

27 1. 5. 3 OA3: Education and Workforce Development ................................

................................ ... 28 1.

6 General Roles of the Award Recipient and NIST ................................ ................................ ..........

30 1. 6. 1 Substantial Involvement of CHIPS R&D ................................

................................ ........... 30 1.

6. 2 Responsibilities of Recipient ................................ ................................

.............................. 30 1. 6.

3 Involvement of NIST and CHIPS R&D ................................ ................................ ..............

31 1. 6. 4 Joint Activities Between Recipient and NIST and CHIPS R&D ................................

........ 31 1. 6.

5 Coordination with other Federal R&D Programs ................................ ............................... 31 1.

7 Broader Impacts ................................ ................................ ................................

............................. 32 1. 7.

1 Commitments to Future Investment ................................ ................................ ....................

32 1. 7. 2 Creating Inclusive Opportunities ................................

................................ ........................ 32 1.

7. 3 Environmental Responsibility ................................ ................................

............................. 33 7 1. 7.

4 Community Impact and Support ................................ ................................ .........................

33 1. 8 Government -Furnished Property (GFP) and Government Furnished Information (GFI) .............. 34 2 FEDERAL AWARD INFORMATION ................................

................................ .............................. 34 2.

1 Funding Availability ................................ ................................ ................................

...................... 34 2. 1.

1 Funding Instrument and Payments ................................ ................................ ......................

34 2. 1. 2 Multi -Year Funding Policy ................................

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34 2. 2 Eligible Uses of Funds ................................ ................................

................................ ................... 34 2.

2. 1 Construction ................................ ................................

................................ ........................ 35 2.

2. 2 Indirect (F&A) Costs ................................ ................................

................................ .......... 35 2.

3 Public Access to CHIPS R&D Research ................................ ................................ .......................

36 2. 4 Fundamental Research ................................ ................................

................................ ................... 36 2.

4. 1 Fundamental Research Declaration ................................ ................................

..................... 36 2. 4.

2 On -Campus Research ................................ ................................ ................................

.......... 36 2. 4.

3 Pre -Publication Reviews ................................ ................................ ................................

..... 37 2. 5 Research Security ................................

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37 2. 5. 1 Research Security Definitions ................................

................................ ............................. 37 2.

5. 2 Authorities ................................ ................................

................................ ........................... 37 2.

5. 3 Requirement for a Research Security Plan or Program ................................ .......................

38 2. 5. 4 Covered Individuals ................................

................................ ................................ ............

39 2. 5. 5 Foreign Entities of Concern ................................

................................ ................................ 40 2.

5. 6 Research Security Review and Risk Determination ................................ ...........................

40 2. 5. 7 Non -Discrimination Policy ................................

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41 2. 5. 8 Potential for Mitigation ................................

................................ ................................ .......

41 2. 5. 9 Requirement for Recipients to Update Research Security -Related Information ................

41 2. 6 Intellectual Property (IP) and Domestic Production ................................ ................................

...... 42 2. 6.

1 Intellectual Property ................................ ................................ ................................

............ 42 2. 6.

2 Domestic Production ................................ ................................ ................................

........... 42 2. 6.

3 Domestic Control ................................ ................................ ................................

................ 43 2. 6.

4 Commercial Viability and Domestic Production Plan (CVDP) ................................ .......... 44 3 ELIGIBILITY INFORMATION ................................

................................ ................................ ........

45 3. 1 Eligible Applicants and Subrecipients ................................ ................................

........................... 45 3. 1.

1 Federally Funded Research and Development Centers ................................ ....................... 46 3.

1. 2 Federal Entities ................................ ................................

................................ ................... 47 3.

1. 3 Individuals and Unincorporated Sole Proprietors ................................ ...............................

47 8 3. 1. 4 Foreign Partners and Foreign Research Activities ................................

.............................. 47 3. 2 Optional Co -investment ................................

................................ ................................ .................

48 3. 3 Allowable Costs ................................ ................................

................................ ............................. 49 4 APPLICATION AND SUBMISSION INFORMATION ................................

................................ ... 49 4.

1 Overview ................................ ................................ ................................

................................ ........ 49 4.

2 Where to obtain an Application Package ................................ ................................ .......................

49 4. 3 Page Count Guidance ................................ ................................

................................ ..................... 50 4.

4 Submission Format ................................ ................................ ................................

........................ 50 4. 4.

1 Amendments ................................ ................................ ................................

....................... 50 4. 4.

2 Proprietary and Sensitive Business Information ................................ ................................ .

50 4. 5 Concept Paper Instructions ................................ ................................

................................ ............ 50 4.

5. 1 Required Forms and Documents ................................ ................................

......................... 51 4. 5.

2 Concept Paper Format and Guidelines ................................ ................................ ................

55 4. 6 Full Application Instructions ................................ ................................

................................ ......... 56 4.

6. 1 Required Forms and Documents ................................ ................................

......................... 56 4. 6.

2 Attachment of Required Documents ................................ ................................ ...................

71 4. 6. 3 Full Application Format and Guidelines ................................

................................ ............. 72 4.

7 Application Replacement Pages ................................ ................................ ................................

.... 74 4. 8 Unique Entity Identifier and System for Award Management (SAM) ................................

.......... 74 4. 9 Submission Dates and Times ................................

................................ ................................ .........

74 4. 9. 1 Concept Papers ................................

................................ ................................ ....................

74 4. 9. 2 Full Applications ................................

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75 4. 10 Intergovernmental Review ................................ ................................

................................ ............. 75 4.

11 Funding Restrictions ................................ ................................ ................................

...................... 75 5 APPLICATION REVIEW INFORMATION ................................ ................................

..................... 75 5. 1 Concept Paper Evaluation Criteria ................................

................................ ................................ .

75 5. 1. 1 Relevance to economic and national security ................................

................................ ..... 75 5.

1. 2 Overall Scientific and Technical Merit ................................ ................................

............... 76 5. 1.

3 Project Management, Resources, and Budget ................................ ................................ .....

76 5. 1. 4 Transition and Impact Strategy ................................

................................ ........................... 77 5.

1. 5 Education and Workforce Development (EWD) ................................ ................................

77 5. 2 Concept Paper Selection Factors ................................ ................................

................................ ... 77 5.

3 Full Application Evaluation Criteria ................................ ................................ ..............................

78 5. 3. 1 Relevance to Economic and National Security ................................

................................ ... 78 9 5.

3. 2 Overall Scientific and Technical Merit ................................ ................................

............... 79 5. 3.

3 Project Management, Resources, and Budget ................................ ................................ .....

79 5. 3. 4 Transition and Impact Strategy ................................

................................ ........................... 80 5.

3. 5 Education and Workforce Development (EWD) ................................ ................................

80 5. 4 Full Application Selection Factors ................................ ................................

................................ . 81 5.

5 Review and Selection Process ................................ ................................ ................................

....... 81 5. 5.

1 Initial Review of Applications ................................ ................................ ............................

82 5. 5. 2 Review of Concept Papers ................................

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82 5. 5. 3 Review of Full Applications ................................

................................ ............................... 83 5.

6 Additional Information ................................ ................................ ................................

.................. 86 5. 6.

1 Safety ................................ ................................ ................................

................................ .. 86 5.

6. 2 Notification to Unsuccessful Applicants ................................ ................................

............. 86 5. 6.

3 Retention of Unsuccessful Applications ................................ ................................ .............

86 6 Federal Award Administration Information ................................ ................................ ........................

86 6. 1 Federal Award Notices ................................ ................................

................................ .................. 86 6.

2 Administrative and National Policy Requirements ................................ ................................ ........

86 6. 2. 1 Terms and Conditions ................................

................................ ................................ .........

86 6. 2. 2 Funding Availability and Limitation of Liability ................................

................................ 87 6. 2.

3 Collaborations with CHIPS R&D and Other Federal Agencies ................................ ......... 87 6.

2. 4 Use of Federal Government -Owned Intellectual Property ................................ ..................

88 6. 2. 5 Export Controls ................................

................................ ................................ ...................

88 6. 3 Reporting ................................ ................................

................................ ................................ .......

89 6. 3. 1 Reporting Requirements ................................

................................ ................................ .....

89 6. 3. 2 Audit Requirements ................................

................................ ................................ ............

90 6. 3. 3 Federal Funding and Accountability Transparency Act of 2006 ................................

........ 90 7 AGENCY CONTACTS ................................ ................................

................................ ...................... 91 8 OTHER INFORMATION ................................

................................ ................................ ..................

91 8. 1 Personal and Business Information ................................ ................................

................................ 91 8. 2 Public Website ................................

................................ ................................ ...............................

92 10 The statutory authorities for the CHIPS AI/AE for Rapid, Industry -informed Sustainable Semiconductor Materials and Processes (CARISSMA) program NOFO are 15 U.S.C. § 4656 (c) and 15 U.S.C. § 4659, as amended .

a The 2022 CHIPS and Science Act appropriated $50 billion to the U.S. Department of Commerce’s (the Department or DOC ) CHIPS for America program to strengthen semiconductor manufacturing in the United States. This amount includes $39 billion for the Department to onshore semiconductor manufacturing through an incentives program and $11 billion to advance U.S. leadership in semiconductor research and development (R&D).

These R&D advances will primarily be realiz ed through the following four programs: the CHIPS National Semiconductor Technology Center (NSTC), the CHIPS National Advanced Packaging Manufacturing Program (NAPMP), the CHIPS Metrology Program, and the CHIPS Manufacturing USA Program (MFG USA).

These investments, across both the R&D and incentives programs, seek to strengthen U.S. competitiveness, support dom estic production and innovation, create good jobs across the country —with working conditions consistent with the Good Jobs Principles published by the Department of Commerce and the U.S. Department of Labor —and advance U.S. economic and national security.

The CARISSMA program will complement these efforts by generating or enhancing sustainable semiconductor materials and processes . Research outputs should prove relevant and translatable to industry, the NSTC, the CHIP S Manufacturing USA Program , and other CHIPS programs.

The competition should further enhance participation in and availability of academic -industry partnerships and research infrastructure for CHIPS Act funded activities and the development of a thriving semiconductor -related AI/AE talent pool . 1. 1.

1 CHIPS R&D Mission and Goals Within the CHIPS for America program, the mission of the National Institute of Standards and Technology (NIST) CHIPS Research and Development Office (CHIPS R&D) is to accelerate the development and commercial deployment of foundational semiconductor technologies by establishing, connecting, and providing access to domestic research efforts, tools, resources, workers, and facilities.

CHIPS R&D aims to achieve the following goals by 2030: • U.S. Technology Leadership : The United States improves its capacity to invent, develop, prototype, manufacture, and deploy the foundational semiconductor technologies of the > aDOC CHIPS activities were authorized by Title XCIX —Creating Helpful Incentives to Produce Semiconductors for America of > the William M.

(Mac) Thornberry National Defense Authorization Act for Fiscal Year 2021 (Pub. L. 116 -283), often referred to > as the CHIP S Act, codified at 15 U.S.C.

§4651 et seq. , as amended.

• Accelerated Ideas to Market : The best ideas achieve commercial scale as quickly and cost effectively as possible ; and • Robust Semiconductor Workforce : Inventors, designers, researchers, developers, engineers, technicians, and staff sustainably meet evolving domestic government and Accelerated discovery , design , and validation of new materials promises critical benefits to the future of the global semiconductor industry.

b,c,d These materials must not only yield higher - performing semiconductor products but also address sustainability concerns challenging the industry, including the use of toxic chemicals, greenhouse gas (GHG) emissions, and water and energy efficiency. However, the deployment of new materials and processes can require years of research, development, testing, and validation.

AI/AE has emerged as a potentially game -changing approach to accelerate materials discovery and development. This NOFO therefore aims to create collaborations between academia and the private sector that are university -led , industry -informed , and relevant to sustainable semiconductor manufacturing.

These collaborations should support the long -term viability of domestic semiconductor manufacturing by accelerating the discovery, design, synthesis, and deployment of new materials and processes ; developing and connecting cutting -edge AI/AE techniques, know -how, and infrastructure; and developing new researchers needed to meet the industry’s technological , economic, and sustainability goals.

If successful, CHIPS R&D investments under this NOFO should demonstrate that new sustainable semiconductor materials and processes, meeting industry needs, can be designed and adopted for industry testing within five years. Further, the investment should a ccelerate a step - change in the number of universities, researchers, and graduates participating in the U.S. semiconductor R&D ecosystem.

The resulting objectives under this NOFO are to : (1) Accelerate research into and delivery of targeted, industry -relevant, sustainable semiconductor materials and processes through the application of AI/AE ; (2) Propagate models for incorporating sustainability metrics into semiconductor industry materials design and discovery, in addition to continued advancement in power, performance, area, cost , or other relevant technology metrics; (3) Expand the capabilities of emerging resea rch institutions ( ERI s) and other emerging R&D participants through cohesive innovative teams of universities, industry, government labs, and other stakeholders; and > bSemiconductor Research Corporation, “MAPT Microelectronics and Advanced Packaging Technologies Roadmap”, 2023.

> Available online at: srcmapt. org/wp -content/uploads/2024/03/SRC -MAPT -Roadmap -2023 -v4. pdf > cAI Aspirations: AI for Sustainable Materials, White House Office of Science and Technology Policy, 2024.

Available online at: > dNational Strategy on Microelectronics Research, A Report by the Subcommittee on Microelectronics Leadership, March 2024. (4) Build an exceptional workforce of university graduates and faculty with AI/AE R&D The anticipated program outcomes, if successful, should prove relevant and translatable to the NSTC, the CHIPS Manufacturing USA Institute, and other CHIPS programs.

For purposes of this NOFO, the terms listed below shall have the following meanings : (1) Applied Research – “Original investigation undertaken in order to acquire new knowledge.

Applied research is, however, directed primarily towards a specific practical (2) AI -enabled autonomous experimentation (AI/AE) – The combination of automated (robotic) hardware for materials synthesis and characterization, AI -powered software and models, and data acquisition, analysis, computational resources, and storage hardware that plan, execute, and evaluate experiments in a utonomous closed loops to achieve accelerated research objectives supplied by human researchers.

2 (3) Basic Research – “Experimental or theoretical work undertaken primarily to acquire new knowledge of the underlying foundations of phenomena and observable facts.

Basic research may include activities with broad or general applications in mind, such as the study of how plant genomes change, but should exclude research directed towards a specific application or requirement, such as the optimization of the genome of a specific crop species.

” 3 (4) Digital Twin – A set of virtual information constructs that mimics the structure, context, and behavior of a natural , engineered , or social system (or system -of -systems). Typically, a digital twin can be dynamically updated with data from its physical twin, has a predictive capability, and informs decisions that realize value.

4 (5) Emerging Research Institution or ERI – An institution of higher education with an established undergraduate or graduate program that conducts less than $50,000,000 per year in Federal research expenditures. 5 The Department of Energy maintains an online list of Institution Designations , including ERIs.

(6) Materials Digital Twin – Either (i) a model of the performance of material in response to changes in its environment, or (ii) a model of the synthesis of a material, and its response to changes in synthesis control variables.

(7) Milestones – Actions or events marking a significant change or stage in developments (8) Phase -specific Target – Derived from applicant -specified SMART Milestones, phase - specific targets inform go/revise/no -go points for the transition from one project phase to the next. Phase -specific targets may address measurable progress toward either Co - optimization Targets, Programmatic Targets, or both.

(9) Project – All activities funded under a single award made under this NOFO, including but not limited to all planning and management; basic and applied research; the development and production of manufactured materials and devices, systems, equipment, tools, and software, as appropriate to the funded work; preparation for 13 commercial viability and domestic production of funded innovations; and education and workforce development activities.

(10) Project Team – Any funded entit y (the applicant and any proposed subrecipients) , as well as unfunded collaborators planned for inclusion in a single proposal under this (11) Recipient – The entity that receives an award directly from a Federal awarding agency to carry out an activity under a financial assistance program .

(12) Research Outputs – The results of research funded under this NOFO, including but not limited to data, models, materials, and processes, such as materials property datasets; predictive algorithms; physically manufactured prototype materials; materials digital twins; and manufacturing sustainability design guidelines and frameworks.

(13) Semiconductor – An integrated electronic device or system, most commonly manufactured using materials such as, but not limited to, silicon, silicon carbide, or III -V compounds, and processes such as, but not limited to, lithography, deposition, and etching.

Such device s and systems include but are not limited to analog and digital electronics, power electronics, and photonics, for memory, processing, sensing, actuation, and communications applications.

(14) Semiconductor manufacturing – All activities encompassed by the semiconductor fabrication, advanced packaging, assembly, and test processes, including but not limited (15) Semiconductor materials – The broad class of materials contained in semiconductor devices and systems ( see “semiconductor” definition) as the result of semiconductor manufacturing (which includes packaging), including materials used in semiconductor manufacturing that do not remain in the final product.

(16) SMART – A framework for writing objectives that are Specific, Measurable, Achievable, Relevant, and Time -Bound and provide the details for how an organization will achieve an objective .

(17) Subrecipient – An entity that is eligible to receive a subaward from a Recipient to carry out activities under an award made under this NOFO , such as research and development activities, education and workforce efforts, and other integral project activities . Vendors selling goods or services in the ordinary course of business are not considered subrecipients for purposes of this NOFO.

(18) Sustainability / Sustainable – The ability to meet the needs of the present without compromising the ability of future generations to meet their own needs.

Sustainability has three primary goals: (1) protecting the environment, (2) protecting human health and safety of individuals and communities, and (3) promoting economic prosperity and In its 2023 Microelectronics and Advanced Packaging Technologies Roadmap, the Semiconductor Research Corporation reported on the demand for innovative, sustainable semiconductor materials and chemistries for current and next generation semiconductors and semiconductor manufacturing.

The Roadmap noted that “tools encompassing co -optimization of performance metrics and environmental, health, and safety metrics will help accelerate the 14 discovery of more sustainable materials and chemicals without compromising the performance of the product. ” 7 Other industry reports, including reports published by the Semiconductor PFAS e Consortium, recognize the need for innovation in sustainable materials.

8 These include identifying safer alternatives to existing semiconductor manufacturing materials to developing more effective abatement technologies that prevent the release of chemicals that are harmful to the environment and human health.

9 As the United States and other nations invest in semiconductor manufacturing, these reports reflect a need for manufacturing and its resulting products to demonstrate both high performance and sustainability.

While AI/AE provides an opportunity to address these dual objectives, the industry must nonetheless tackle co -existing (1) economic pressure to address sustainability; (2) difficulty optimizing across sustainability and performance metrics at the accelerated timelines necessary for impact and competitive edge ; and (3) the limited AI/AE infrastructure and workforce. 1. 3.

1 Challenge: Economic Pressure Semiconductor manufacturing requires significant amounts of both water and energy, while using chemicals considered harmful to human health, if released.

Examples are as follows: • The average chip fabrication plant uses 10 million gallons of ultrapure water every day 10 , , the equivalent of 33,000 U.S. homes’ consumption ;12 • Depending on the plant, electricity consumption represents between 5% and 30% of its operating costs, totaling $20 -$30 million per year.

A typical semiconductor plant uses as much energy in a year as about 50,000 homes ;13 and • In 2022, the electronics manufacturing industry was responsible for 5 million metric tons of CO 2-equivalent emissions from fluorinated gases.

14 Given the environmental impact of the semiconductor fabrication process, regulators, manufacturers, and customers have sought more sustainable practices and solutions, including to reduce manufacturing and operating costs as well as litigation and supply c hain risks.

For • Prominent semiconductor companies have targeted water reuse/restore/recycle of up to 75 % or reductions in water usage reductions by up to 33% ;15 • At least t hree manufacturers have announced significant energy consumption reduction, including targets for energy per unit produced, as well significant GHG reduction • One major PFAS supplier is planning to exit the market due to shifting liability .

19 Ano ther PFAS supplier ha s pledged to phase out certain PFAS related products and processes . 20 Regulatory concerns have raised supply chain risks, with no known alternatives currently existing for many PFAS -containing materials used in the semiconductor industry. 21 > ePerfluoroalkyl and polyfluoroalkyl substances.

When considering the full product lifecycle, semiconductor products prove even more energy - intensive with high environmental impacts. For instance, U.S. data centers comprise roughly 2% of total U.S. electricity usage, according to the Department of Energy . 22 1.

3. 2 Challenge: Materials Co -optimization and Time to Deployment Traditional methods for discovery and deployment of new semiconductor materials —with a focus on improving semiconductor performance while decreasing power usage, physical area, and cost —can require years , even decades, of research, development, testing and validation before deployment.

23 Material characterization experiments, which validate and inform models, are time and labor intensive and often the rate -limiting step in a material validation campaign. Moreover, a lack of validating experiments limits current models of materials design.

Including materials sustainability will likely increase these challenges ; limit the material candidate pool due to some candidates’ toxicity, effects on human health , and environmental impact; and increase the time required for materials discovery and validation.

By way of example, when considering the potential for PFAS replacements to impact multiple parts of the precisely - calibrated semiconductor supply chain, the Semiconductor Industry Association (SIA) concluded that timelines for adoption of non -PFAS materials adoption can range from — • 3 to 4 years, if there is an existing non -PFAS alternative available that can be demonstrated to provide adequate performance for a specific application; • 3 to 15 years, where existing non -PFAS alternative may be viable but require tooling and/or process changes; and • Up to 25 years for new chemicals or the development of alternative approaches to manufacturing devices.

24 1. 3. 3 Challenge: Limited Research Workforce In its recent workshop report on AI/AE, an Interagency Working Group of the Materials Genome Initiative (MGI) found an essential role for researchers in “supporting industrial development and aligning fundamental research with broader industry goals, such as carbon neutrality and manufacturability.

” 25 The Working Group’s report further highlighted a demand for graduates trained in autonomous experimentation and materials R&D, with “the combination of AI/ML coding skills and the specific specialization in their respective materials field.

” 26 However, the same report estimated that the United States had few institutions ready to conduct fully autonomous AI/AE research in electronics and photonics materials , much less research relevant to semiconductor materials sustainability.

This presents a challenge for acquiring the needed research staff, particularly given SIA’s projection of 27,300 semiconductor industry engineering roles remaining unfilled due to an insufficient number of graduates in relevant technical fields. These include 9,900