Cross-disciplinary Semiconductor Research (CSR)

Cross-disciplinary Semiconductor Research (CSR) is sponsored by Semiconductor Research Corporation (SRC) GRC. The CSR program solicits grant applications to foster exploratory, multi-disciplinary, longer-term university research leading to novel high-payoff solutions for challenges faced by the semiconductor industry.

Cross-disciplinary Semiconductor Research (CSR) - SRC Learn about our core values 2030 Decadal Plan for Semiconductors Research Experience for Undergrads Broadening Participation Pledge Our commitment to sustainability Learn about the Liaison program Use LinkedIn to find Research Scholars Learn about Pillar Science Industry resources for SRC researchers Launch Pillar Science research platform Find Talent in Pillar Science SRC Research Scholars: Getting Started Call for Grant Applications in Cross-disciplinary Semiconductor Research (CSR) Grant Application Guidelines SRC GRC is soliciting grant applications in Cross-disciplinary Semiconductor Research.

The goal of CSR is to foster exploratory, multi-disciplinary, longer-term university research leading to novel high-payoff solutions for the science and technology challenges faced by the semiconductor industry at and beyond the time horizons of the International Technology Roadmap for Semiconductors (ITRS).

Successful CSR projects will offer innovative and, possibly, disruptive solutions to the challenge of continuing the exponential gains in cost/performance benefits provided by the semiconductor industry for the foreseeable future, and may lead to novel applications for this industry. The SRC CSR Program specifically solicits exploratory proposals in three related but distinct areas in 2012.

I) Emerging Technology, and II) Emerging Design, and III) Emerging Materials. An indication of SRC interests in these three areas is outlined in the following: Continued dimensional and functional scaling of CMOS is driving information processing technology into a broadening spectrum of new applications.

Longer Horizon Technologies include end-of-the Roadmap CMOS solutions, projected to scale below 10 nm, and several new alternative devices for existing or new functions that may help to sustain the historical integrated circuit scaling cadence and reduction of cost/function into future decades.

There is a strong interest in new devices for digital, RF, analog and mixed-signal applications, and in new technologies for heterogeneous integration of multiple functions (a. k. a.

“More than Moore”). Topics of interest include but are not limited to (for a more complete list of potential research topics please refer to the Emerging Research Devices Chapter of the 2011 International Technology Roadmap for Semiconductors, http://www. itrs.

net/Links/2011ITRS/Home2011. htm ): FETs utilizing non-traditional materials (III-V, Ge…) with efficient n- and p-channel devices using the same material system Tunnel FET, nanowire FETs, NEMS, and other emerging logic devices Emerging memory devices, e.g. Redox memory, Mott memory, etc. Emerging devices based on new physical principles for RF, analog and mixed-signal circuits.

Examples include Tunnel FET, spin-torque oscillator, memristor, vibrating-Body FET etc. Radically new ideas for efficient light sources for optical interconnects Exploring nanoscale physics and new materials Longer Horizon Design needs are driven by considerations such as increasing complexity, emergence of new prospective enabling technologies, the massive data challenge etc. Emerging devices based on new physical principles need to be explored in the circuit and system design context to better understand their potential.

Many emerging application drivers require SoC/SiP multi-technologies, i.e. the design of a heterogeneous system in a single chip or in a single package. For example, sensor chip design needs orders of magnitude reduction in their operating power from where we are today.

New hardware solutions will be needed, such as e.g. neuromorphic circuits for fast and energy-efficient data extraction; new nonvolatile memory architectures for power savings etc. For testing of multi-technology chips, e.g. sensor chips, it is crucial to eliminate the need for custom actuation-based testers & handlers, in order to minimize cost.

Ideally ‘design for (no) test’ solutions are needed which includes self-test/self-calibration. For mixed-signal/RF VLSI circuits, there is a growing need to operate in the 100 GHz+ regime where design methodologies are immature, thus radical new ideas are needed to develop design capabilities for design at mm-wave frequencies on standard CMOS process.

Topics of interest include but are not limited to (for a more complete list of topics please refer to the 2011 International Technology Roadmap for Semiconductors, in particular the chapters on System Drivers, Design, RF and Analog/Mixed-signal Technologies and MEMS - http://www. itrs. net/Links/2011ITRS/Home2011.

htm ): Compact modeling of advanced logic and analog devices Architectures for enabling exponential increase in communication bandwidth including new embedded nonvolatile memory, I/Os and network-on-chip approaches etc. Solutions for transfer of massive blocks of data to, from and across the chip Target data transfer rate – >50-100 Gbps without significant increase in operating power Hardware and software solutions for data fusion Conversion of massive data into actionable information Exploring emerging devices based on new physical principles for data converters, i.e. analog-to-digital and digital-to-analog e.g. memristive devices for data conversion Simulation-based mixed-signal/RF design at extremely high frequencies (100 GHz+) Fundamental circuit blocks New Methods for modeling of interconnects and passive components at >100 GHz Sensor circuits design and test Targeting orders of magnitude reduction in their operating power New hardware solutions, such as e.g. neuromorphic circuits for fast and energy-efficient data extraction Solutions for embedded cryptoprocessor as part of the sensor chip Self-test methodologies based on the reciprocity of most physical mechanisms underlying sensors This topic includes material properties, synthetic methods, metrology and modeling required for emerging research nanoelectronic devices, including analog devices, sensors, energy sources etc. Proposals in the broad cross-disciplinary area of materials research are sought, that address Difficult Challenges in emerging research materials technologies.

These challenges and projected research requirements are summarized in the 2011 ITRS chapters on Interconnects and Emerging Research Materials ( http://www. itrs. net/Links/2011ITRS/Home2011.

htm ).

Topics of interest include but are not limited to: Emerging interconnect materials for beyond copper and carbon (please refer to the Emerging Interconnect Solutions section in the Interconnects Chapter of the 2011 ITRS) Metal silicides, silver etc. Metallic Phonon Engineering Metallic Geometric Resonance Additive manufacturing for sub 10 nm structures e.g. combining methods of Directed Self Assembly, selective deposition, etc. for etch-free pattern transfer Thermoelectric materials for on-chip energy sources and cooling technologies.

Grant Application Guidelines Responses are limited to 3 pages , using no less than a 10-point font, and MUST BE SUBMITTED VIA THE SRC WEB SITE by MONDAY, June 4th, 3 PM EDT/12 PM PDT . Non-compliance with these guidelines may exclude your grant application from consideration.

Please include the following identifying information in your grant application: Telephone number and e-mail address Please address the following in your grant application: Approximately 100 word executive summary Problem to be addressed - explain the rationale for the project in terms of the semiconductor industry needs Objective - what do you plan to do?

Novelty - the basic concept and discuss the role of cross-disciplinary research in providing a unique solution to the problem addressed Approach - strategy for addressing the problem Research output - identify possible research products of a successful research program IP - disclose blocking background intellectual property Open Call for Grant Applications Deadline to Submit Grant Applications Monday, June 4, 2012 - 3 PM EDT/12 PM PDT Notification of Final Program Selection Results Wednesday, January 1, 2013 Please direct all technical questions to Dr. Victor Zhirnov , (victor.

zhirnov@src. org, 919-941-9454). All other questions should be directed to Leslie Faiers ( leslie.

faiers@src. org , 919-941-9455). Participating Universities 4819 Emperor Blvd, Suite 300 Durham, NC 27703 Voice: (919) 941-9400 Fax: (919) 941-9450 Access to information on this website may be limited to member companies, participating agencies, and qualified researchers.

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