1,000+ Opportunities
Find the right grant
Search federal, foundation, and corporate grants with AI — or browse by agency, topic, and state.
This listing may be outdated. Verify details at the official source before applying.
Find similar grantsEnabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is sponsored by National Science Foundation (NSF). NSF supports education, training, and community infrastructure for end-to-end integrated micro/nano-electronic circuit semiconductor chip design.
Get a weekly digest of new grants like this
A free weekly digest of new foundation and federal funding opportunities as they're added to Granted. Unsubscribe anytime.
Or search similar grants →Extracted from the official opportunity page/RFP to help you evaluate fit faster.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) | NSF - U.S. National Science Foundation Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) Archived funding opportunity This document has been archived.
Important information for proposers and award recipients All proposals must be submitted in accordance with the requirements specified in the funding opportunity and in the Proposal & Award Policies & Procedures Guide (PAPPG) and its supplements . All NSF grants and cooperative agreements are subject to the applicable set of NSF award terms and conditions . NSF has updated its research security policies for NSF funded projects.
Supports education, training and community infrastructure for end-to-end integrated micro/nano-electronic circuit semiconductor chip design. Integrated micro/nano-electronic circuits (ICs) are a foundational technology that enable advancements in artificial intelligence, 5G/6G communication, security, scientific computing, quantum computing, and more.
The economic competitiveness, technological leadership, and national security of the United States depend on a future workforce at the forefront of IC design and fabrication, spanning IC researchers, IC designers, and IC fabrication engineers and technicians.
Since IC design and fabrication must deal with staggering complexities to meet system functionality, performance, and energy objectives, offering students at all levels with hands-on experiences designing and fabricating IC chips is imperative. The needs of research and education communities in this domain have been widely recognized by a range of reports, including those derived from NSF-sponsored workshops.
Prospective PIs for this solicitation are encouraged to read the following reports: NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities ( https://nsfedaworkshop. nd. edu/assets/432289/nsf20_eda_workshop_report.
pdf ) NSF Integrated Circuit Research, Education and Workforce Development Workshop ( https://nsf-ic-education. com/NSF_IC_Workshop_Final_Report. pdf ) NSF Workshop on CMOS+X Technologies ( https://e3s-center.
berkeley. edu/nsf-workshop-cmosx/cmos-x-report/ ) This solicitation seeks proposals to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation.
The infrastructure should provide licensing, access, and maintenance of (i) commercial and/or open-source EDA tools necessary for the end-to-end IC chip design and verification process, and (ii) design PDK/IPs at various CMOS technology nodes (potentially including emerging technologies), as well as support for multi-project-chip (MPC) integration.
Further, proposals should include efforts to develop, curate, and host educational/tutorial materials on the entire IC chip design flow to help train the next generation of IC designers and researchers. PIs interested in submitting a proposal to this program are strongly encouraged to discuss their plans with cognizant Program Officers.
January 22, 2024 - Chip Design Hub Program Webinar Awards made through this program Browse projects funded by this program Map of recent awards made through this program Directorate for Computer and Information Science and Engineering (CISE) Division of Computing and Communication Foundations (CISE/CCF) Division of Computer and Network Systems (CISE/CNS)
According to the current listing, eligibility includes: Non-profit, non-academic organizations and institutions of higher education. Confirm the full requirements in the official notice before applying.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is funded by National Science Foundation (NSF). Verify program details on the funder's official page before applying.
Start from the official opportunity page linked in this listing — it carries the sponsor's submission instructions.
TCUP lists eight funding tracks and roughly $10.3M a year, but the October 14, 2026 deadline applies to only three of them — CHAI, Pre-TI, and TCUP Partnerships — and each carries a restriction that disqualifies most applicants. Here is the track-by-track math.
Read articleNSF 26-513 makes roughly $100 million available for up to 10 State and Regional AI Infrastructure Hubs at $4M to $12M each over five years. One award per state or multi-state region. One proposal per organization. And NSF is not buying you GPUs — it funds the coordination, the workforce and the faculty training, while the compute has to come from partners you have to already have.
Read articleAs of September 12, NSF had obligated $6.3 billion across 6,200 grants versus $8.1 billion and 8,600 last year. AHRQ has made 61 awards. Judge Allison Burroughs ordered the government to report by September 28 on whether IES will obligate $180 million before it expires. Here is what actually happens to the money on October 1 — and what it means for your FY2027 application.
Read article