1,000+ Opportunities
Find the right grant
Search federal, foundation, and corporate grants with AI — or browse by agency, topic, and state.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is sponsored by National Science Foundation (NSF). This solicitation aims to dramatically lower the barriers to accessing state-of-the-art electronic design automation (EDA) tools, process design kits (PDKs), and design intellectual property (IP) cores for students and academic researchers, and to enable students at various leve…
Get alerted about grants like this
Get emailed when new opportunities from “National Science Foundation (NSF)” or related funders appear. Free, weekly, unsubscribe anytime.
Or search similar grants →Extracted from the official opportunity page/RFP to help you evaluate fit faster.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) | NSF - U.S. National Science Foundation Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) Archived funding opportunity This document has been archived.
Important information for proposers and award recipients All proposals must be submitted in accordance with the requirements specified in the funding opportunity and in the Proposal & Award Policies & Procedures Guide (PAPPG) and its supplements . All NSF grants and cooperative agreements are subject to the applicable set of NSF award terms and conditions . NSF has updated its research security policies for NSF funded projects.
Supports education, training and community infrastructure for end-to-end integrated micro/nano-electronic circuit semiconductor chip design. Integrated micro/nano-electronic circuits (ICs) are a foundational technology that enable advancements in artificial intelligence, 5G/6G communication, security, scientific computing, quantum computing, and more.
The economic competitiveness, technological leadership, and national security of the United States depend on a future workforce at the forefront of IC design and fabrication, spanning IC researchers, IC designers, and IC fabrication engineers and technicians.
Since IC design and fabrication must deal with staggering complexities to meet system functionality, performance, and energy objectives, offering students at all levels with hands-on experiences designing and fabricating IC chips is imperative. The needs of research and education communities in this domain have been widely recognized by a range of reports, including those derived from NSF-sponsored workshops.
Prospective PIs for this solicitation are encouraged to read the following reports: NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities ( https://nsfedaworkshop. nd. edu/assets/432289/nsf20_eda_workshop_report.
pdf ) NSF Integrated Circuit Research, Education and Workforce Development Workshop ( https://nsf-ic-education. com/NSF_IC_Workshop_Final_Report. pdf ) NSF Workshop on CMOS+X Technologies ( https://e3s-center.
berkeley. edu/nsf-workshop-cmosx/cmos-x-report/ ) This solicitation seeks proposals to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation.
The infrastructure should provide licensing, access, and maintenance of (i) commercial and/or open-source EDA tools necessary for the end-to-end IC chip design and verification process, and (ii) design PDK/IPs at various CMOS technology nodes (potentially including emerging technologies), as well as support for multi-project-chip (MPC) integration.
Further, proposals should include efforts to develop, curate, and host educational/tutorial materials on the entire IC chip design flow to help train the next generation of IC designers and researchers. PIs interested in submitting a proposal to this program are strongly encouraged to discuss their plans with cognizant Program Officers.
January 22, 2024 - Chip Design Hub Program Webinar Awards made through this program Browse projects funded by this program Map of recent awards made through this program Directorate for Computer and Information Science and Engineering (CISE) Division of Computing and Communication Foundations (CISE/CCF) Division of Computer and Network Systems (CISE/CNS)
According to the current listing, eligibility includes: Academic institutions and researchers. NSF expects to fund up to two Chip Design Hub awards under this program. Confirm the full requirements in the official notice before applying.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is funded by National Science Foundation (NSF). Verify program details on the funder's official page before applying.
Start from the official opportunity page linked in this listing — it carries the sponsor's submission instructions.
NVIDIA Graduate Fellowship Program is a grant from NVIDIA providing up to $60,000 per award to PhD students conducting research that advances accelerated computing and its applications. Now in its 25th year, the program invites nominations from doctoral students pushing the boundaries of artificial intelligence, robotics, autonomous vehicles, and related fields. Recipients receive not only research funding but also access to NVIDIA technology, products, and engineering expertise, along with a mandatory in-person summer internship. Students are nominated by their faculty advisors and selected based on academic achievement and research area alignment.
CalSEED Concept Award is a grant from the California Energy Commission that provides $150,000 in funding to early-stage clean energy innovators in California. The program targets individuals, businesses, and nonprofits developing hardware, software, or integrated solutions at Technology Readiness Levels 2-4. Eligible technology areas rotate each cycle and have included battery recycling and reuse, long-duration energy storage, medium- and heavy-duty vehicle electrification, industrial electrification, and advanced EV charging. Applicants must be located in California, have under $1 million in private funding, and propose innovations that benefit California ratepayers. Concept Award winners also receive professional development resources and access to accelerator programs, and may compete for a subsequent $450,000 Prototype Award.
NIST SBIR Phase I - Advanced Manufacturing and Robotics is sponsored by National Institute of Standards and Technology. NIST SBIR Phase I - Advanced Manufacturing and Robotics is a grant from the National Institute of Standards and Technology (NIST) that funds small businesses with innovative research and technology ideas in advanced manufacturing and robotics.
NSF's rebuilt SBIR/STTR program (NSF 26-510) pairs a $305,000 Phase I with a brand-new Strategic Breakthrough award worth up to $30 million for the strongest Phase II companies. The next Project Pitch deadline is July 27, 2026. Here is how the non-dilutive funding ladder now works, why the Project Pitch gate decides everything, and how a founder should sequence the next twelve months.
Read articleOMB's proposed rewrite of 2 CFR Part 200 would bar political appointees from deferring to peer reviewers and require senior-appointee sign-off on every discretionary grant. NIH new awards are already down about 34% in 2026. Here is what the merit-review changes actually say, how 'Gold Standard Science' becomes a scoring lever, why R1 universities are being written out of some solicitations, and what principal investigators and research offices should do before October 1.
Read articleAfter a disruptive pause, NSF has reopened its SBIR/STTR programs with $250 million for deep-tech startups — including a $40M scientific-instrumentation pilot and a new Strategic Breakthrough track that can reach $30 million. The first Project Pitch deadline is July 27, 2026. Here is how the reopened pipeline works, why the Project Pitch is the real gate, and how founders should sequence a submission before the window narrows.
Read article