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Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is sponsored by U.S. National Science Foundation (NSF). This solicitation aims to reduce barriers to accessing state-of-the-art Electronic Design Automation (EDA) tools, Process Design Kits (PDKs), and Intellectual Property (IP) cores for students and academic researchers, and to enable students at various levels to design Integrated…
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Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) | NSF - U.S. National Science Foundation Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) Archived funding opportunity This document has been archived.
NSF's implementation of the revised 2 CFR NSF Financial Assistance awards (grants and cooperative agreements) made on or after October 1, 2024, will be subject to the applicable set of award conditions, dated October 1, 2024, available on the NSF website . These terms and conditions are consistent with the revised guidance specified in the OMB Guidance for Federal Financial Assistance published in the Federal Register on April 22, 2024.
Important information for proposers All proposals must be submitted in accordance with the requirements specified in this funding opportunity and in the NSF Proposal & Award Policies & Procedures Guide (PAPPG) that is in effect for the relevant due date to which the proposal is being submitted. It is the responsibility of the proposer to ensure that the proposal meets these requirements.
Submitting a proposal prior to a specified deadline does not negate this requirement.
Updates to NSF Research Security Policies On July 10, 2025, NSF issued an Important Notice providing updates to the agency's research security policies, including a research security training requirement, Malign Foreign Talent Recruitment Program annual certification requirement, prohibition on Confucius institutes and an updated FFDR reporting and submission timeline.
Supports education, training and community infrastructure for end-to-end integrated micro/nano-electronic circuit semiconductor chip design. Integrated micro/nano-electronic circuits (ICs) are a foundational technology that enable advancements in artificial intelligence, 5G/6G communication, security, scientific computing, quantum computing, and more.
The economic competitiveness, technological leadership, and national security of the United States depend on a future workforce at the forefront of IC design and fabrication, spanning IC researchers, IC designers, and IC fabrication engineers and technicians.
Since IC design and fabrication must deal with staggering complexities to meet system functionality, performance, and energy objectives, offering students at all levels with hands-on experiences designing and fabricating IC chips is imperative. The needs of research and education communities in this domain have been widely recognized by a range of reports, including those derived from NSF-sponsored workshops.
Prospective PIs for this solicitation are encouraged to read the following reports: NSF Workshop on Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities ( https://nsfedaworkshop. nd. edu/assets/432289/nsf20_eda_workshop_report.
pdf ) NSF Integrated Circuit Research, Education and Workforce Development Workshop ( https://nsf-ic-education. com/NSF_IC_Workshop_Final_Report. pdf ) NSF Workshop on CMOS+X Technologies ( https://e3s-center.
berkeley. edu/nsf-workshop-cmosx/cmos-x-report/ ) This solicitation seeks proposals to establish and manage a community infrastructure that supports the entire IC chip design process beginning from behavior/structural description at the Register Transfer Level (RTL) or above to GDSII fabrication mask file generation.
The infrastructure should provide licensing, access, and maintenance of (i) commercial and/or open-source EDA tools necessary for the end-to-end IC chip design and verification process, and (ii) design PDK/IPs at various CMOS technology nodes (potentially including emerging technologies), as well as support for multi-project-chip (MPC) integration.
Further, proposals should include efforts to develop, curate, and host educational/tutorial materials on the entire IC chip design flow to help train the next generation of IC designers and researchers. PIs interested in submitting a proposal to this program are strongly encouraged to discuss their plans with cognizant Program Officers.
January 22, 2024 - Chip Design Hub Program Webinar Awards made through this program Browse projects funded by this program Map of recent awards made through this program Directorate for Computer and Information Science and Engineering (CISE) Division of Computing and Communication Foundations (CISE/CCF) Division of Computer and Network Systems (CISE/CNS)
According to the current listing, eligibility includes: Proposals may only be submitted by non-profit, non-academic organizations (independent museums, observatories, research laboratories, professional societies, etc.). Confirm the full requirements in the official notice before applying.
The current listing shows up to $1.6 million per year for up to 5 years (up to two awards anticipated with total funding of $10,000,000). Verify award ceilings, matching requirements, and allowable costs in the official notice.
Enabling Access to the Semiconductor Chip Ecosystem for Design, Fabrication, and Training (Chip Design Hub) is funded by U.S. National Science Foundation (NSF). Verify program details on the funder's official page before applying.
Yes — this listing is flagged as national in scope, so applicants across the U.S. may apply, subject to the sponsor's other eligibility criteria.
Start from the official opportunity page linked in this listing — it carries the sponsor's submission instructions.
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