1,000+ Opportunities
Find the right grant
Search federal, foundation, and corporate grants with AI — or browse by agency, topic, and state.
Intelligent Design of Electronic Assets (IDEA) program is sponsored by Defense Advanced Research Projects Agency (DARPA). The IDEA program aims to develop a general purpose hardware compiler for no-human-in-the-loop translation of source code or schematic to physical layout for System-on-Chips (SoCs), System-In-Packages (SIPs), and Printed Circuit Boards (PCBs) in less than 24 hours.
Get a weekly digest of new grants like this
A free weekly digest of new foundation and federal funding opportunities as they're added to Granted. Unsubscribe anytime.
Or search similar grants →Extracted from the official opportunity page/RFP to help you evaluate fit faster.
Intelligent Design of Electronic Assets Department of War organization.
IDEA: Intelligent Design of Electronic Assets IDEA: Intelligent Design of Electronic Assets Next-generation intelligent systems supporting Department of Defense (DoD) applications like artificial intelligence, autonomous vehicles, shared spectrum communication, electronic warfare, and radar require processing efficiency that is orders of magnitude beyond what is available through current commercial electronics.
Reaching the performance levels required by these DoD applications however will require developing highly complex system-on-chip (SoC) platforms that leverage the most advanced integrated circuit technologies. Despite advances in electronic design automation (EDA) tools, the complexity associated with the design and verification of integrated circuits (ICs) continues to increase rapidly due in part to the steady progress of Moore's Law.
To help meet design requirements, commercial electronics manufacturers creating advanced hardware solutions will employ large teams of designers, each with expertise in a specific facet of the design flow. For the DoD however, researchers and development teams do not have the resources available to effectively execute such a strategy, resulting in hardware design cycles that are two to three times longer than commercial establishments.
To overcome the design expertise gap and keep pace with the exponential increase in chip complexity, the Intelligent Design of Electronic Assets (IDEA) program seeks to develop a general purpose hardware compiler for no-human-in-the-loop translation of source code or schematic to physical layout (GDSII) for SoCs, System-In-Packages (SIPs), and Printed Circuit Boards (PCBs) in less than 24 hours.
The program aims to leverage advances in applied machine learning, optimization algorithms, and expert systems to create a compiler that could allow users with no prior design expertise to complete physical design at the most advanced technology nodes.
The goal of the IDEA program is to provide the DoD with a path to rapid development of next-generation electronic systems without the need for large design teams, reducing the cost and complexity barriers associated with leading-edge electronic design. This program is now complete This content is available for reference purposes. This page is no longer maintained.
According to the current listing, eligibility includes: Organizations capable of performing research and development in electronic design automation (EDA) tools, applied machine learning, optimization algorithms, and expert systems. Confirm the full requirements in the official notice before applying.
Intelligent Design of Electronic Assets (IDEA) program is funded by Defense Advanced Research Projects Agency (DARPA). Verify program details on the funder's official page before applying.
Start from the official opportunity page linked in this listing — it carries the sponsor's submission instructions.
DPA26BZ06-DV023 is a Direct-to-Phase-II SBIR paying $700,000 over 18 months plus a $500,000 option. The physics demands 256x more transmit power than the systems that qualify you to compete, and DARPA will not accept modeling alone as proof. Here is the eligibility wall, the five engineering problems, and who can realistically win it before the October 21 close.
Read articleRelease 6's SBIR topics got the attention. Its three STTR topics — SHIELDER, fuel-flexible electric propulsion, and hypersonic wind tunnel noise diagnostics — are all Direct-to-Phase-II, all require a research institution to perform at least 30 percent of the work, and all close October 21, 2026. The feasibility gates are the real filter.
Read articleDPA26BZ06-DV026 offers $300,000 at Phase I or $1,800,000 as a single Direct-to-Phase-II tranche with no options. The deliverable is a simulated auction market that measures whether AI agents deceive, collude, or manipulate the humans they serve — measured entirely from the outside. Here is the 90% efficiency gate, the team composition most bidders will get wrong, and why this topic sits in DARPA's biology office.
Read article