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NSF 18-588: NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) | NSF - U.S. National Science Foundation Archived funding opportunity This solicitation is archived. Important information for proposers and award recipients All proposals must be submitted in accordance with the requirements specified in the funding opportunity and in the Proposal & Award Policies & Procedures Guide (PAPPG) and its supplements .

All NSF grants and cooperative agreements are subject to the applicable set of NSF award terms and conditions . NSF has updated its research security policies for NSF funded projects. NSF 18-588: NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) Download the solicitation (PDF, 0.

7mb) National Science Foundation Directorate for Computer & Information Science & Engineering Division of Computing and Communication Foundations Intel Labs University Collaboration Office Full Proposal Deadline(s) (due by 5 p. m.

submitter's local time): important Information And Revision Notes Any proposal submitted in response to this solicitation should be submitted in accordance with the revised NSF Proposal & Award Policies & Procedures Guide (PAPPG) ( NSF 18-1 ), which is effective for proposals submitted, or due, on or after January 29, 2018.

summary Of Program Requirements NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) The confluence of transistor scaling, increases in the number of architecture designs per process generation , the slowing of clock frequency growth, and recent success in research exploiting thread-level parallelism (TLP) and data-level parallelism (DLP) all point to an increasing opportunity for innovative microarchitecture techniques and methodologies in delivering performance growth in the future.

The NSF/Intel Partnership on Foundational Microarchitecture Research will support transformative microarchitecture research targeting improvements in instructions per cycle (IPC) . This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of existing microarchitectural structures.

Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation.

Advances in these areas promise to provide significant performance improvements that continue the trends characterized by Moore’s Law. Cognizant Program Officer(s): Please note that the following information is current at the time of publishing. See program website for any updates to the points of contact.

Yuanyuan Yang, Program Director, CCF, Matt Haycock, Center Executive Sponsor, Vice President, matthew. haycock@intel.

com Hong Wang, Center Managing Sponsor, Intel Fellow, Jeff Parkhurst, Center Program Director, Applicable Catalog of Federal Domestic Assistance (CFDA) Number(s): --- Computer and Information Science and Engineering Anticipated Type of Award: Standard Grant or Continuing Grant or Intel Agreement (i.e., Contract, Grant or Gift) Estimated Number of Awards: 5 Approximately 5 awards are anticipated, each up to $500,000 and up to 3 years in duration, subject to the availability of funds and quality of proposals received.

Anticipated Funding Amount: $2,500,000 subject to the availability of funds and quality of proposals received. Who May Submit Proposals: Proposals may only be submitted by the following: Institutions of Higher Education (IHEs) - Two- and four-year IHEs (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members.

Special Instructions for International Branch Campuses of US IHEs: If the proposal includes funding to be provided to an international branch campus of a US institution of higher education (including through use of subawards and consultant arrangements), the proposer must explain the benefit(s) to the project of performance at the international branch campus, and justify why the project activities cannot be performed at the US campus.

There are no restrictions or limits. Limit on Number of Proposals per Organization: There are no restrictions or limits. Limit on Number of Proposals per PI or Co-PI: 1 An individual may participate as PI, co-PI, or senior personnel in no more than one proposal submitted in response to this solicitation.

In the event that an individual exceeds this limit, the first proposal received within the limits will be accepted based on the earliest date and time of proposal submission (i.e., the first proposal received will be accepted and the remainder will be returned without review). No exceptions will be made.

This limit on the number of proposals per PI, co-PI, or senior personnel applies only to this NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) program solicitation. Proposal Preparation and Submission Instructions A.

Proposal Preparation Instructions Letters of Intent: Not required Preliminary Proposal Submission: Not required Full Proposals submitted via FastLane: NSF Proposal and Award Policies and Procedures Guide (PAPPG) guidelines apply. The complete text of the PAPPG is available electronically on the NSF website at: https://www. nsf.

gov/publications/pub_summ. jsp? ods_key=pappg .

Full Proposals submitted via Grants. gov: NSF Grants. gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.

gov guidelines apply (Note: The NSF Grants. gov Application Guide is available on the Grants. gov website and on the NSF website at: https://www.

nsf. gov/publications/pub_summ. jsp?

ods_key=grantsgovguide ). Cost Sharing Requirements: Inclusion of voluntary committed cost sharing is prohibited. Indirect Cost (F&A) Limitations: Other Budgetary Limitations: Other budgetary limitations apply.

Please see the full text of this solicitation for further information. Full Proposal Deadline(s) (due by 5 p. m.

submitter's local time): Proposal Review Information Criteria National Science Board approved criteria apply. Award Administration Information Additional award conditions apply. Please see the full text of this solicitation for further information.

Additional reporting requirements apply. Please see the full text of this solicitation for further information. Today’s applications and language runtime environments, which employ and host highly demanding algorithms across multiple domains and span both server- and client-side deployments, yield significant opportunity for microarchitecture technique innovations.

The confluence of transistor scaling, increases in the number of architecture generations per process generation, the slowing of clock frequency growth, and recent success in research exploiting TLP and DLP all point to an increasing opportunity for innovative microarchitecture techniques in delivering performance growth in the future.

Instruction-level parallelism (ILP) improvements face fundamentally difficult constraints, e.g., branch misprediction and cache misses. Overcoming these constraints, while difficult, promises to bring substantial increases in IPC. The NSF/Intel Partnership on Foundational Microarchitecture Research will support microarchitecture research targeting transformative improvements in IPC .

This solicitation seeks microarchitecture technique innovations beyond simplistic, incremental scaling of the existing microarchitectural structures.

Specifically, FoMR seeks to advance research that has the following characteristics: (1) high IPC techniques ranging from microarchitecture to code generation; (2) “microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and (3) techniques to support efficient compiler code generation.

Success in this area promises to provide significant performance improvements that continue the trends characterized by Moore’s Law.

Advancing process development in order to sustain the economies of scale of the semiconductor business is becoming very costly; for each new process generation, more than two generations of architecture designs are being introduced to maintain the compound annual growth rate (CAGR) in performance anticipated by the marketplace.

Hence, this program seeks to support the architecture and design community in pursuing transformative research to address this challenge. Improving ILP still faces fundamentally difficult constraints, e.g., branch misprediction and cache misses. Overcoming these constraints, while difficult, promises to bring substantial increases in IPC.

While these constraints have remained for a very long time, there are presently opportunities for significant advances. Prior to multicore designs, only those microarchitecture mechanisms that could introduce performance improvement commensurate with die area and power investment were selected for implementation for the mainstream microprocessor. Now, multicore systems with more than a dozen cores are quite common.

When the system runs a single threaded program (or runs a critical section in a multi-threaded program), die area and power investment from the entire chip and all of the bandwidth from system memory are available for boosting single-thread performance. An example of such a strategy is boosting voltage and frequency for the core that is active, redirecting a large fraction of the system power budget and bandwidth to that core.

This program will support microarchitecture research targeting improvements in IPC, with a particular emphasis on techniques beyond simplistic scaling of the existing microarchitecture structures. Success in this area promises to provide significant performance improvements to continue the performance cadence promised by and commensurate with the transistor density that Moore’s Law characterizes.

Of particular interest are: This program seeks the following high level research objectives: High IPC techniques spanning from microarchitecture to code generation innovations; “Microarchitecture turbo” techniques that marshal chip resources and system memory bandwidth to accelerate sequential or single-threaded programs; and Techniques to support efficient compiler code generation .

In order to address the previously stated objectives, FoMR seeks research proposals that explore one or more of the following areas (note that this list is not exhaustive): Microarchitecture and code generation techniques to boost branch prediction accuracy puts an upper bound on the ILP achievable by programs. There are still branches that are very hard to predict, and these offer an opportunity to push the upper bound higher.

Similar situations apply to memory disambiguation and cache management: on average, these are working well, but some behavior remains hard to predict. Cache miss ratios are low for many programs but are high for some other programs; they also place an upper bound on the achievable ILP. Instruction scheduling and organization of execution resources to enable efficient, very-large instruction window processors.

Improving ILP requires the instruction window to be enlarged substantially. A very-large instruction window creates challenges in complexity and lengthens critical path delay. Next-generation prefetchers with vastly higher coverage than possible today, especially in light of emerging memory technologies.

Emerging memory technologies, while non-volatile, have read latencies that are often higher than dynamic random-access memory (DRAM), and write latencies that are much higher than DRAM. In addition, they often have write endurance problems. Techniques to redesign prefetching so that coverage can be increased substantially are desired.

Techniques to redesign prefetching so that it works well with emerging memory technologies are desired as well. Cache management techniques that work efficiently across multiple levels of cache hierarchy comprising heterogeneous memories [e.g., static random-access memory (SRAM), high bandwidth memory (HBM), or traditional DRAM].

These may include cache allocation, replacement, bypassing, prefetching, etc., in the context of heterogeneous memories Machine learning and data analytics-based approach to improving microarchitecture design and runtime tuning. Machine learning and data analytics provide new tools for improved ability to understand and optimize microarchitecture and program behavior.

These tools may be utilized for runtime tuning of microarchitecture parameters so that they can be adapted to execute programs more efficiently. Utilization of new microarchitecture building blocks , such as reconfigurable logic to boost IPC.

As fine-grain reconfigurable fabric [e.g., classic field-programmable gate arrays (FPGA)] and coarse-grain reconfigurable arrays (CGRA) become integrated into microprocessors, they have potential to become the foundational implementation building block akin to SRAM and the register file to enable novel microarchitecture structures for general-purpose microprocessors.

For example, they can be used to construct workload-specific branch predictors or memory prefetchers that comprehend salient patterns in control flow behavior or memory access behavior unique to workload execution, in particular, cloud computing. Enabling such deployment-aware, workload-specific predictors that can be programmed and updated in-the-field is akin to a traditional microcode update in the virtualized environment.

Microarchitecture support for efficient compiler code generation beyond trace generation and traditional performance counter profiling. There is a need for microarchitectures to provide higher-fidelity feedback to the compiler, so that the compiler can generate more efficient code, either for recompilation purposes or for just-in-time optimizations. Criticality-oriented design and techniques.

Critical path delay limits ILP and the overall performance of computer systems. Techniques that reduce the critical path delay, and at the same time exploit slacks on non-critical paths in order to boost ILP, are desired. Microprocessor and process co-optimization .

Microprocessors and processes are often designed separately. However, there are opportunities for co-design, which in turn would enhance optimization, and these should be exploited when possible and practical to improve ILP. FoMR further encourages proposals to pursue open source approaches that will facilitate reproducibility and reuse of research results by the broader microarchitecture research community.

Proposing teams are encouraged to outline their plans in this regard as part of the Project Description and Data Management Plan sections of their proposals.

Anticipated Type of Award: Standard Grant or Continuing Grant or Intel Agreement (i.e., Contract, Grant or Gift) Estimated Number of Awards: Approximately 5 awards are anticipated, each up to $500,000 and up to 3 years in duration, subject to the availability of funds and quality of proposals received. Anticipated Funding Amount: $2,500,000, subject to the availability of funds and quality of proposals received.

Estimated program budget, number of awards and average award size/duration are subject to the availability of funds. iv. Eligibility Information Who May Submit Proposals: Proposals may only be submitted by the following: Institutions of Higher Education (IHEs) - Two- and four-year IHEs (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members.

Special Instructions for International Branch Campuses of US IHEs: If the proposal includes funding to be provided to an international branch campus of a US institution of higher education (including through use of subawards and consultant arrangements), the proposer must explain the benefit(s) to the project of performance at the international branch campus, and justify why the project activities cannot be performed at the US campus.

There are no restrictions or limits. Limit on Number of Proposals per Organization: There are no restrictions or limits. Limit on Number of Proposals per PI or Co-PI: An individual may participate as PI, co-PI, or senior personnel in no more than one proposal submitted in response to this solicitation.

In the event that an individual exceeds this limit, the first proposal received within the limits will be accepted based on the earliest date and time of proposal submission (i.e., the first proposal received will be accepted and the remainder will be returned without review). No exceptions will be made.

This limit on the number of proposals per PI, co-PI, or senior personnel applies only to this NSF/Intel Partnership on Foundational Microarchitecture Research (FoMR) program solicitation. Additional Eligibility Info: v. Proposal Preparation And Submission Instructions A.

Proposal Preparation Instructions Full Proposal Preparation Instructions : Proposers may opt to submit proposals in response to this Program Solicitation via Grants. gov or via the NSF FastLane system.

Full proposals submitted via FastLane: Proposals submitted in response to this program solicitation should be prepared and submitted in accordance with the general guidelines contained in the NSF Proposal & Award Policies & Procedures Guide (PAPPG). The complete text of the PAPPG is available electronically on the NSF website at: https://www. nsf.

gov/publications/pub_summ. jsp? ods_key=pappg .

Paper copies of the PAPPG may be obtained from the NSF Publications Clearinghouse, telephone (703) 292-7827 or by e-mail from nsfpubs@nsf. gov . Proposers are reminded to identify this program solicitation number in the program solicitation block on the NSF Cover Sheet For Proposal to the National Science Foundation.

Compliance with this requirement is critical to determining the relevant proposal processing guidelines. Failure to submit this information may delay processing. Full proposals submitted via Grants.

gov: Proposals submitted in response to this program solicitation via Grants. gov should be prepared and submitted in accordance with the NSF Grants. gov Application Guide: A Guide for the Preparation and Submission of NSF Applications via Grants.

gov . The complete text of the NSF Grants. gov Application Guide is available on the Grants.

gov website and on the NSF website at: ( https://www. nsf. gov/publications/pub_summ.

jsp? ods_key=grantsgovguide ). To obtain copies of the Application Guide and Application Forms Package, click on the Apply tab on the Grants.

gov site, then click on the Apply Step 1: Download a Grant Application Package and Application Instructions link and enter the funding opportunity number, (the program solicitation number without the NSF prefix) and press the Download Package button. Paper copies of the Grants. gov Application Guide also may be obtained from the NSF Publications Clearinghouse, telephone (703) 292-7827 or by e-mail from nsfpubs@nsf.

gov . In determining which method to utilize in the electronic preparation and submission of the proposal, please note the following: Collaborative Proposals. All collaborative proposals submitted as separate submissions from multiple organizations must be submitted via the NSF FastLane system.

PAPPG Chapter II. D. 3 provides additional information on collaborative proposals.

See PAPPG Chapter II. C. 2 for guidance on the required sections of a full research proposal submitted to NSF.

Please note that the proposal preparation instructions provided in this program solicitation may deviate from the PAPPG instructions. A proposal title must begin with the acronym FoMR , followed by a colon, and then the title of the proposed project.

If you submit a proposal as part of a set of collaborative proposals, the title of the proposal should begin with FoMR , followed by a colon, then " Collaborative Research ", followed by a colon, and then the title of the proposed project. For example, if you are submitting a collaborative set of proposals, the title of each proposal would be FoMR: Collaborative Research: Title.

For all collaborative projects, project descriptions must be comprehensive and well-integrated, and should make a convincing case that the collaborative contributions of the project team will be greater than the sum of each of their individual contributions.

In the Supplementary Documents Section, upload the following information where relevant: 1) A list of Project Personnel and Partner Institutions (note: in collaborative proposals, the lead institution should provide this information for all participants) : Provide current, accurate information for all personnel and institutions involved in the project.

NSF staff will use this information in the merit review process to manage reviewer selection. The list should include all PIs, Co-PIs, Senior Personnel, paid/unpaid Consultants or Collaborators, Subawardees, Postdocs, and project-level advisory committee members. This list should be numbered and include (in this order) Full name, Organization(s), and Role in the project, with each item separated by a semi-colon.

Each person listed should start a new numbered line.

For example: Mary Smith; XYZ University; PI John Jones; University of PQR; Senior Personnel Jane Brown; XYZ University; Postdoc Bob Adams; ABC Community College; Paid Consultant Susan White; DEF Corporation; Unpaid Collaborator Tim Green; ZZZ University; Subawardee 2) Collaboration Plans (if applicable; note: in collaborative proposals, the lead institution should provide this information for all participants) : Since the success of collaborative research efforts are known to depend on thoughtful coordination mechanisms that regularly bring together the various participants of the project, all FoMR projects that include more than one investigator must include a Collaboration Plan of up to 2 pages .

The length and degree of detail provided in the Collaboration Plan should be commensurate with the complexity of the proposed project.

Where appropriate, the Collaboration Plan might include: 1) the specific roles of the project participants in all organizations involved; 2) information on how the project will be managed across all the investigators, institutions, and/or disciplines; 3) identification of the specific coordination mechanisms that will enable cross-investigator, cross-institution, and/or cross-discipline scientific integration (e.g., yearly workshops, graduate student exchanges, project meetings at conferences, use of videoconferences, software repositories, etc.); and 4) specific references to the budget line items that support collaboration and coordination mechanisms.

If a FoMR project with more than one investigator does not include a Collaboration Plan of up to 2 pages, that proposal will be returned without review. 3) Postdoctoral Researcher Mentoring Plan (if applicable): Each proposal that requests funding to support postdoctoral researchers must include, as a supplementary document, a description of the mentoring activities that will be provided for such individuals.

In no more than one page, the mentoring plan must describe the mentoring that will be provided to all postdoctoral researchers supported by the project, irrespective of whether they reside at the submitting organization, any subawardee organization, or at any organization participating in a simultaneously submitted collaborative project.

Please be advised that if required, FastLane will not permit submission of a proposal that is missing a Postdoctoral Researcher Mentoring Plan. See Chapter II. C.

2. j of the Proposal and Awards Policies and Procedures Guide (PAPPG) for further information about the implementation of this requirement. 4) Data Management Plan (required): Proposals must include a supplementary document of no more than two pages labeled "Data Management Plan."

This supplementary document should describe how the proposal will conform to NSF policy on the dissemination and sharing of research results. See Chapter II. C.

2. j of the PAPPG for full policy implementation . For additional information see: https://www.

nsf. gov/bfa/dias/policy/dmp. jsp .

For specific guidance for proposals submitted to the Directorate for Computer and Information Science and Engineering (CISE) see: https://www. nsf. gov/cise/cise_dmp.

jsp . 5) Documentation of collaborative arrangements of significance to the proposal through Letters of Collaboration: There are two types of collaboration, one involving individuals/organizations that are included in the budget, and the other involving individuals/organizations that are not included in the budget. Collaborations that are included in the budget should be described in the Project Description.

Any substantial collaboration with individuals/organizations not included in the budget should be described in the Facilities, Equipment and Other Resources section of the proposal (see PAPPG Chapter II. C. 2.

i). In either case, whether or not the collaborator is included in the budget, a letter of collaboration from each named participating organization other than the submitting lead, non-lead, and/or subawardee institutions should be provided at the time of submission of the proposal.

Such letters should explicitly state the nature of the collaboration, appear on the organization's letterhead and be signed by the appropriate organizational representative. These letters must not otherwise deviate from the restrictions and requirements set forth in the PAPPG , Chapter II. C.

2. j. Please note that letters of support may not be submitted.

Such letters do not document collaborative arrangements of significance to the project, but primarily convey a sense of enthusiasm for the project and/or highlight the qualifications of the PI or co-PI. Reviewers will be instructed not to consider these letters of support in reviewing the merits of the proposal. No other Supplementary Documents, except as permitted by the NSF PAPPG , are allowed.

Collaborators and Other Affiliations Information : Proposers should follow the guidance specified in Chapter II. C. 1.

e of the NSF PAPPG. Grants. gov Users: The COA information must be provided through use of the COA template and uploaded as a PDF attachment.

Note the distinction to the list of Project Personnel and Partner Institutions specified above under Supplementary Documents: the listing of all project participants is collected by the project lead and entered as a Supplementary Document, which is then automatically included with all proposals in a project.

The Collaborators and Other Affiliations are entered for each participant within each proposal and, as Single Copy Documents, are available only to NSF staff. Inclusion of voluntary committed cost sharing is prohibited. Other Budgetary Limitations: It is expected that PIs, co-PIs, and students of funded projects will participate in annual PI meetings.

All such expenses are to be included in project budgets for the duration of the project. Intel will support travel and the expenses associated with the annual meetings for Intel participants. Intel will support all travel-related expenses for PIs, co-PIs, and students as well as meeting expenses for any additional meetings/retreats that Intel requests and organizes in association with this solicitation.

Full Proposal Deadline(s) (due by 5 p. m. submitter's local time): D.

FastLane/Grants. gov Requirements For Proposals Submitted Via FastLane: To prepare and submit a proposal via FastLane, see detailed technical instructions available at: https://www. fastlane.

nsf. gov/a1/newstan. htm .

For FastLane user support, call the FastLane Help Desk at 1-800-673-6188 or e-mail fastlane@nsf. gov . The FastLane Help Desk answers general technical questions related to the use of the FastLane system.

Specific questions related to this program solicitation should be referred to the NSF program staff contact(s) listed in Section VIII of this funding opportunity. For Proposals Submitted Via Grants. gov: Before using Grants.

gov for the first time, each organization must register to create an institutional profile. Once registered, the applicant's organization can then apply for any federal grant on the Grants. gov website.

Comprehensive information about using Grants. gov is available on the Grants. gov Applicant Resources webpage: http://www.

grants. gov/web/grants/applicants. html .

In addition, the NSF Grants. gov Application Guide (see link in Section V. A) provides instructions regarding the technical preparation of proposals via Grants.

gov. For Grants. gov user support, contact the Grants. gov Contact Center at 1-800-518-4726 or by email: support@grants.

gov . The Grants. gov Contact Center answers general technical questions related to the use of Grants.

gov. Specific questions related to this program solicitation should be referred to the NSF program staff contact(s) listed in Section VIII of this solicitation. Submitting the Proposal: Once all documents have been completed, the Authorized Organizational Representative (AOR) must submit the application to Grants. gov and verify the desired funding opportunity and agency to which the application is submitted.

The AOR must then sign and submit the application to Grants. gov. The completed application will be transferred to the NSF FastLane system for further processing. Proposers that submitted via FastLane are strongly encouraged to use FastLane to verify the status of their submission to NSF.

For proposers that submitted via Grants. gov, until an application has been received and validated by NSF, the Authorized Organizational Representative may check the status of an application on Grants. gov. After proposers have received an e-mail notification from NSF, Research.

gov should be used to check the status of an application. vi. NSF Proposal Processing And Review Procedures Proposals received by NSF are assigned to the appropriate NSF program for acknowledgement and, if they meet NSF requirements, for review.

All proposals are carefully reviewed by a scientist, engineer, or educator serving as an NSF Program Officer, and usually by three to ten other persons outside NSF either as ad hoc reviewers, panelists, or both, who are experts in the particular fields represented by the proposal. These reviewers are selected by Program Officers charged with oversight of the review process.

Proposers are invited to suggest names of persons they believe are especially well qualified to review the proposal and/or persons they would prefer not review the proposal. These suggestions may serve as one source in the reviewer selection process at the Program Officer's discretion. Submission of such names, however, is optional.

Care is taken to ensure that reviewers have no conflicts of interest with the proposal. In addition, Program Officers may obtain comments from site visits before recommending final action on proposals. Senior NSF staff further review recommendations for awards.

A flowchart that depicts the entire NSF proposal and award process (and associated timeline) is included in PAPPG Exhibit III-1. A comprehensive description of the Foundation's merit review process is available on the NSF website at: https://www. nsf.

gov/bfa/dias/policy/merit_review/ . One of the strategic objectives in support of NSF's mission is to foster integration of research and education through the programs, projects, and activities it supports at academic and research institutions. These institutions must recruit, train, and prepare a diverse STEM workforce to advance the frontiers of science and participate in the U.S. technology-based economy.

NSF's contribution to the national innovation ecosystem is to provide cutting-edge research under the guidance of the Nation's most creative scientists and engineers. NSF also supports development of a strong science, technology, engineering, and mathematics (STEM) workforce by investing in building the knowledge that informs improvements in STEM teaching and learning.

NSF's mission calls for the broadening of opportunities and expanding participation of groups, institutions, and geographic regions that are underrepresented in STEM disciplines, which is essential to the health and vitality of science and engineering. NSF is committed to this principle of diversity and deems it central to the programs, projects, and activities it considers and supports. A.

Merit Review Principles and Criteria The National Science Foundation strives to invest in a robust and diverse portfolio of projects that creates new knowledge and enables breakthroughs in understanding across all areas of science and engineering research and education.

To identify which projects to support, NSF relies on a merit review process that incorporates consideration of both the technical aspects of a proposed project and its potential to contribute more broadly to advancing NSF's mission "to promote the progress of science; to advance the national health, prosperity, and welfare; to secure the national defense; and for other purposes."

NSF makes every effort to conduct a fair, competitive, transparent merit review process for the selection of projects. 1. Merit Review Principles These principles are to be given due diligence by PIs and organizations when preparing proposals and managing projects, by reviewers when reading and evaluating proposals, and by NSF program staff when determining whether or not to recommend proposals for funding and while overseeing awards.

Given that NSF is the primary federal agency charged with nurturing and supporting excellence in basic research and education, the following three principles apply: All NSF projects should be of the highest quality and have the potential to advance, if not transform, the frontiers of knowledge. NSF projects, in the aggregate, should contribute more broadly to achieving societal goals.

These "Broader Impacts" may be accomplished through the research itself, through activities that are directly related to specific research projects, or through activities that are supported by, but are complementary to, the project. The project activities may be based on previously established and/or innovative methods and approaches, but in either case must be well justified.

Meaningful assessment and evaluation of NSF funded projects should be based on appropriate metrics, keeping in mind the likely correlation between the effect of broader impacts and the resources provided to implement projects. If the size of the activity is limited, evaluation of that activity in isolation is not likely to be meaningful.

Thus, assessing the effectiveness of these activities may best be done at a higher, more aggregated, level than the individual project. With respect to the third principle, even if assessment of Broader Impacts outcomes for particular projects is done at an aggregated level, PIs are expected to be accountable for carrying out the activities described in the funded project.

Thus, individual projects should include clearly stated goals, specific descriptions of the activities that the PI intends to do, and a plan in place to document the outputs of those activities. These three merit